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1 4 tmsiqueira
-------------------------------------------------------------------------------
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-- Title      : mux
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-- Project    : 
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-------------------------------------------------------------------------------
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-- File       : mux.vhd
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-- Author     : 
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-- Company    : 
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-- Created    : 2003-11-28
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-- Last update: 2003-12-05
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-- Platform   : 
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-------------------------------------------------------------------------------
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-- Description: Multiplixador de 2-1
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-------------------------------------------------------------------------------
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-- Copyright (c) 2003 
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Date        Version  Author  Description
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-- 2003-11-28  1.0      tmsiqueira      Created
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-------------------------------------------------------------------------------
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  library ieee;
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  use ieee.std_logic_1164.all;
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  entity mux is
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    generic (
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      width : natural);
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    port (
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      inRa : in  std_logic_vector(WIDTH-1 downto 0);
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      inIa : in  std_logic_vector(WIDTH-1 downto 0);
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      inRb : in  std_logic_vector(WIDTH-1 downto 0);
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      inIb : in  std_logic_vector(WIDTH-1 downto 0);
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      outR : out std_logic_vector(WIDTH-1 downto 0);
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      outI : out std_logic_vector(WIDTH-1 downto 0);
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                clk  : in  std_logic;
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      sel  : in  std_logic);
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  end mux;
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  architecture mux of mux is
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  begin  -- mux
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--    outR <= inRa when (sel='0') else (others => 'Z');
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--              outR <= inRb when (sel='1') else (others => 'Z');
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--    outI <= inIa when (sel='0') else (others => 'Z');
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--              outI <= inIb when (sel='1') else (others => 'Z');
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--       with sel select
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--      outR <= inRa when '0',
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--              inRb when others;
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--       with sel select
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--      outI <= inIa when '0',
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--              inIb when others;
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   process (clk)
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        begin
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           if clk'event and clk='1' then
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                   case sel is
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                           when '0' =>
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                                   outR <= inRa;
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                                        outI <= inIa;
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                                when '1' =>
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                                   outR <= inRb;
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                                        outI <= inIb;
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                                when others =>
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                                   null;
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                        end case;
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                end if;
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        end process;
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  end mux;

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