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1 4 tmsiqueira
-------------------------------------------------------------------------------
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-- Title      : ram.vhd
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-- Project    : 
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-------------------------------------------------------------------------------
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-- File       : ram.vhd
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-- Author     : 
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-- Company    : 
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-- Created    : 2003-12-05
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-- Last update: 2003-12-05
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-- Platform   : 
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-------------------------------------------------------------------------------
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-- Description: Bloco de ram para armazenar a parte real e a imaginaria.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2003 
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Date        Version  Author  Description
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-- 2003-12-05  1.0      tmsiqueira      Created
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-------------------------------------------------------------------------------
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  library IEEE;
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  use IEEE.std_logic_1164.all;
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  entity ram is
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    generic (
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        width      : natural;
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        depth      : natural;
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        Addr_width : natural);
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      port (
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          clkin   : in  std_logic;      -- clock para a porta de entrada
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          wen     : in  std_logic;      -- write enable
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          addrin  : in  std_logic_vector(Addr_width-1 downto 0);  -- endereco de entrada
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          dinR    : in  std_logic_vector(width-1 downto 0);   -- imag data in
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          dinI    : in  std_logic_vector(width-1 downto 0);   -- real data in
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          clkout  : in  std_logic;      -- clock para a porta de saida
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          addrout : in  std_logic_vector(Addr_width-1 downto 0);  -- endereco de leitura
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          doutR   : out std_logic_vector(width-1 downto 0);   -- real data out
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          doutI   : out std_logic_vector(width-1 downto 0));  -- imag data out
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  end ram;
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  architecture ram of ram is
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    component blockdram
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      generic (
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        depth  : natural;
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        Dwidth : natural;
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        Awidth : natural);
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      port (
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        clkin   : in  std_logic;
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        wen     : in  std_logic;
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        addrin  : in  std_logic_vector(Awidth-1 downto 0);
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        din     : in  std_logic_vector(Dwidth-1 downto 0);
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        clkout  : in  std_logic;
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        addrout : in  std_logic_vector(Awidth-1 downto 0);
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        dout    : out std_logic_vector(Dwidth-1 downto 0));
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    end component;
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  begin  -- ram
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    Real_ram : blockdram
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      generic map (
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        depth  => depth,
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        Dwidth => width,
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        Awidth => Addr_width)
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      port map (
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        clkin   => clkin,
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        wen     => wen,
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        addrin  => addrin,
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        din     => dinR,
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        clkout  => clkout,
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        addrout => addrout,
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        dout    => doutR);
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    Imag_ram : blockdram
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      generic map (
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        depth  => depth,
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        Dwidth => width,
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        Awidth => Addr_width)
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      port map (
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        clkin   => clkin,
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        wen     => wen,
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        addrin  => addrin,
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        din     => dinI,
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        clkout  => clkout,
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        addrout => addrout,
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        dout    => doutI);
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  end ram;

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