OpenCores
URL https://opencores.org/ocsvn/ofdm/ofdm/trunk

Subversion Repositories ofdm

[/] [ofdm/] [branches/] [avendor/] [ram_control.vhd] - Blame information for rev 13

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 tmsiqueira 
library IEEE;
2 
use IEEE.STD_LOGIC_1164.all;
3 
use IEEE.STD_LOGIC_ARITH.all;
4 
use IEEE.STD_LOGIC_SIGNED.all;
5 
 
6 
entity ram_control is
7 
  generic (
8 
    Tx_nRX : natural := 0;
9 
    stage  : natural := 3);
10 
 
11 
  port (
12 
    clk          : in  std_logic;
13 
    rst          : in  std_logic;
14 
    Gen_state    : in  std_logic_vector(2*stage+2 downto 0);
15 
    mem_bk       : in  std_logic;
16 
    addrout_in   : out std_logic_vector(stage*2-Tx_nRX downto 0);
17 
    wen_proc     : out std_logic;
18 
    addrin_proc  : out std_logic_vector(stage*2-1 downto 0);
19 
    addrout_proc : out std_logic_vector(stage*2-1 downto 0);
20 
    wen_out      : out std_logic;
21 
    addrin_out   : out std_logic_vector(stage*2-1 downto 0));
22 
 
23 
 
24 
end ram_control;
25 
 
26 
architecture ram_control of ram_control is
27 
 
28 
  function counter2addr(
29 
    counter : std_logic_vector;
30 
    mask1   : std_logic_vector;
31 
    mask2   : std_logic_vector
32 
    ) return std_logic_vector is
33 
    variable result : std_logic_vector(counter'range);
34 
  begin
35 
    for n in mask1'range loop
36 
      if mask1(n) = '1' then
37 
        result( 2*n+1 downto 2*n ) := counter( 1 downto 0 );
38 
      elsif mask2(n) = '1' and n /= STAGE-1 then
39 
        result( 2*n+1 downto 2*n ) := counter( 2*n+3 downto 2*n+2 );
40 
      else
41 
        result( 2*n+1 downto 2*n ) := counter( 2*n+1 downto 2*n );
42 
      end if;
43 
    end loop;
44 
    return result;
45 
  end counter2addr;
46 
 
47 
  function outcounter2addr(counter : std_logic_vector) return std_logic_vector is
48 
    variable result : std_logic_vector(counter'range);
49 
  begin
50 
    for n in 0 to STAGE-1 loop
51 
      result( 2*n+1 downto 2*n ) := counter( counter'high-2*n downto counter'high-2*n-1 );
52 
    end loop;
53 
    return result;
54 
  end outcounter2addr;
55 
 
56 
  alias state   : std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
57 
  alias counter : std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
58 
 
59 
  constant FFTDELAY    : integer := 13+2*STAGE;
60 
  constant FACTORDELAY : integer := 6;
61 
  constant OUTDELAY    : integer := 9;
62 
 
63 
-- read
64 
  signal rmask1, rmask2 : std_logic_vector( STAGE-1 downto 0 );
65 
-- proc
66 
  signal wmask1, wmask2 : std_logic_vector( STAGE-1 downto 0 );
67 
  signal wcounter       : std_logic_vector( STAGE*2-1 downto 0 );
68 
-- out
69 
  signal outcounter     : std_logic_vector( STAGE*2-1 downto 0 );
70 
 
71 
begin
72 
 
73 
-- Read
74 
  Tx_read : if Tx_nRx = 1 generate
75 
    readaddr : process( clk, rst )
76 
      variable aux_addrout     : std_logic_vector(stage*2-1 downto 0);
77 
      variable aux_addrout_abs : std_logic_vector(stage*2-1 downto 0);
78 
    begin
79 
      if rst = '1' then
80 
        addrout_in      <= ( others => '0' );
81 
        addrout_proc    <= ( others => '0' );
82 
        aux_addrout     := ( others => '0' );
83 
        aux_addrout_abs := ( others => '0' );
84 
        rmask1          <= ( others => '0' );
85 
        rmask2          <= ( others => '0' );
86 
      elsif clk'event and clk = '1' then
87 
        if unsigned(state) = 0 and signed(counter) = 0 then
88 
          rmask1(STAGE-1)          <= '1';
89 
          rmask1(STAGE-2 downto 0) <= (others => '0');
90 
          rmask2(STAGE-1)          <= '0';
91 
          rmask2(STAGE-2 downto 0) <= (others => '1');
92 
        elsif signed(counter) = -1 then
93 
          rmask1 <= '0'&rmask1( STAGE-1 downto 1 );
94 
          rmask2 <= '0'&rmask2( STAGE-1 downto 1 );
95 
        end if;
96 
        aux_addrout     := counter2addr(counter, rmask1, rmask2);
97 
        aux_addrout_abs := abs(aux_addrout);
98 
        if unsigned(state) = 0 then
99 
          if mem_bk = '0' then
100 
            addrout_in <= aux_addrout_abs;
101 
          else
102 
            addrout_in <= aux_addrout_abs+32;
103 
          end if;
104 
        end if;
105 
        addrout_proc <= aux_addrout;
106 
      end if;
107 
    end process readaddr;
108 
  end generate;
109 
 
110 
  Rx_read : if Tx_nRx = 0 generate
111 
    readaddr : process( clk, rst )
112 
      variable aux_addrout : std_logic_vector(stage*2 downto 0);
113 
    begin
114 
      if rst = '1' then
115 
        addrout_in   <= ( others => '0' );
116 
        addrout_proc <= ( others => '0' );
117 
        aux_addrout  := ( others => '0' );
118 
        rmask1       <= ( others => '0' );
119 
        rmask2       <= ( others => '0' );
120 
      elsif clk'event and clk = '1' then
121 
        if unsigned(state) = 0 and signed(counter) = 0 then
122 
          rmask1(STAGE-1)          <= '1';
123 
          rmask1(STAGE-2 downto 0) <= (others => '0');
124 
          rmask2(STAGE-1)          <= '0';
125 
          rmask2(STAGE-2 downto 0) <= (others => '1');
126 
        elsif signed(counter) = -1 then
127 
          rmask1 <= '0'&rmask1( STAGE-1 downto 1 );
128 
          rmask2 <= '0'&rmask2( STAGE-1 downto 1 );
129 
        end if;
130 
        aux_addrout := '0'&counter2addr(counter, rmask1, rmask2);
131 
        if unsigned(state) = 0 and mem_bk = '1' then
132 
          addrout_in <= aux_addrout+64;
133 
        else
134 
          addrout_in <= aux_addrout;
135 
        end if;
136 
        addrout_proc <= aux_addrout(stage*2-1 downto 0);
137 
      end if;
138 
    end process readaddr;
139 
  end generate;
140 
 
141 
 
142 
-- Escrita em proc
143 
 
144 
  writeaddr_proc : process( clk, rst )
145 
  begin
146 
    if rst = '1' then
147 
      addrin_proc <= ( others => '0' );
148 
      wcounter    <= ( others => '0' );
149 
      wmask1      <= ( others => '0' );
150 
      wmask2      <= ( others => '0' );
151 
    elsif clk'event and clk = '1' then
152 
      if unsigned(state) = 0 and unsigned(counter) = FFTDELAY-1 then
153 
        wmask1(STAGE-1)          <= '1';
154 
        wmask1(STAGE-2 downto 0) <= (others => '0');
155 
        wmask2(STAGE-1)          <= '0';
156 
        wmask2(STAGE-2 downto 0) <= (others => '1');
157 
      elsif unsigned(counter) = FFTDELAY-1 then
158 
        wmask1 <= '0'&wmask1( STAGE-1 downto 1 );
159 
        wmask2 <= '0'&wmask2( STAGE-1 downto 1 );
160 
      end if;
161 
      if unsigned(state) < STAGE and unsigned(counter) = FFTDELAY-1 then
162 
        wcounter <= ( others => '0' );
163 
      else
164 
        wcounter <= unsigned(wcounter)+1;
165 
      end if;
166 
      addrin_proc <= counter2addr(wcounter, wmask1, wmask2 );
167 
    end if;
168 
  end process writeaddr_proc;
169 
 
170 
  writeen_proc : process( clk, rst )
171 
  begin
172 
    if rst = '1' then
173 
      wen_proc <= '0';
174 
    elsif clk'event and clk = '1' then
175 
      if unsigned(state) = 0 and unsigned(counter) = FFTDELAY then
176 
        wen_proc <= '1';
177 
      elsif unsigned(state) = STAGE-1 and unsigned(counter) = FFTDELAY then
178 
        wen_proc <= '0';
179 
      end if;
180 
    end if;
181 
  end process writeen_proc;
182 
 
183 
-- Escrite em OutRam
184 
 
185 
  writeaddr_out : process( clk, rst )
186 
  begin
187 
    if rst = '1' then
188 
      outcounter <= (others => '0');
189 
    elsif clk'event and clk = '1' then
190 
      if unsigned(state) = stage-1 and unsigned(counter) = OUTDELAY then
191 
        outcounter <= (others => '0');
192 
      else
193 
        outcounter <= unsigned(outcounter)+1;
194 
      end if;
195 
    end if;
196 
  end process writeaddr_out;
197 
 
198 
  addrin_out <= outcounter2addr(outcounter);
199 
 
200 
  writeen_out : process( clk, rst )
201 
  begin
202 
    if rst = '1' then
203 
      wen_out <= '0';
204 
    elsif clk'event and clk = '1' then
205 
      if unsigned(state) = STAGE-1 and unsigned(counter) = OUTDELAY then
206 
        wen_out <= '1';
207 
      elsif unsigned(outcounter) = 63 then
208 
        wen_out <= '0';
209 
      end if;
210 
    end if;
211 
  end process writeen_out;
212 
end ram_control;
213 
 
214 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.