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1 4 tmsiqueira 
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_SIGNED.all;
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entity ram_control is
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  generic (
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    Tx_nRX : natural := 0;
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    stage  : natural := 3);
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  port (
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    clk          : in  std_logic;
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    rst          : in  std_logic;
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    Gen_state    : in  std_logic_vector(2*stage+2 downto 0);
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    mem_bk       : in  std_logic;
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    addrout_in   : out std_logic_vector(stage*2-Tx_nRX downto 0);
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    wen_proc     : out std_logic;
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    addrin_proc  : out std_logic_vector(stage*2-1 downto 0);
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    addrout_proc : out std_logic_vector(stage*2-1 downto 0);
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    wen_out      : out std_logic;
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    addrin_out   : out std_logic_vector(stage*2-1 downto 0));
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end ram_control;
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architecture ram_control of ram_control is
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  function counter2addr(
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    counter : std_logic_vector;
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    mask1   : std_logic_vector;
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    mask2   : std_logic_vector
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    ) return std_logic_vector is
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    variable result : std_logic_vector(counter'range);
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  begin
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    for n in mask1'range loop
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      if mask1(n) = '1' then
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        result( 2*n+1 downto 2*n ) := counter( 1 downto 0 );
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      elsif mask2(n) = '1' and n /= STAGE-1 then
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        result( 2*n+1 downto 2*n ) := counter( 2*n+3 downto 2*n+2 );
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      else
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        result( 2*n+1 downto 2*n ) := counter( 2*n+1 downto 2*n );
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      end if;
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    end loop;
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    return result;
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  end counter2addr;
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  function outcounter2addr(counter : std_logic_vector) return std_logic_vector is
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    variable result : std_logic_vector(counter'range);
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  begin
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    for n in 0 to STAGE-1 loop
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      result( 2*n+1 downto 2*n ) := counter( counter'high-2*n downto counter'high-2*n-1 );
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    end loop;
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    return result;
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  end outcounter2addr;
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  alias state   : std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
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  alias counter : std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
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  constant FFTDELAY    : integer := 13+2*STAGE;
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  constant FACTORDELAY : integer := 6;
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  constant OUTDELAY    : integer := 9;
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-- read
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  signal rmask1, rmask2 : std_logic_vector( STAGE-1 downto 0 );
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-- proc
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  signal wmask1, wmask2 : std_logic_vector( STAGE-1 downto 0 );
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  signal wcounter       : std_logic_vector( STAGE*2-1 downto 0 );
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-- out
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  signal outcounter     : std_logic_vector( STAGE*2-1 downto 0 );
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begin
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-- Read
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  Tx_read : if Tx_nRx = 1 generate
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    readaddr : process( clk, rst )
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      variable aux_addrout     : std_logic_vector(stage*2-1 downto 0);
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      variable aux_addrout_abs : std_logic_vector(stage*2-1 downto 0);
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    begin
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      if rst = '1' then
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        addrout_in      <= ( others => '0' );
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        addrout_proc    <= ( others => '0' );
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        aux_addrout     := ( others => '0' );
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        aux_addrout_abs := ( others => '0' );
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        rmask1          <= ( others => '0' );
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        rmask2          <= ( others => '0' );
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      elsif clk'event and clk = '1' then
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        if unsigned(state) = 0 and signed(counter) = 0 then
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          rmask1(STAGE-1)          <= '1';
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          rmask1(STAGE-2 downto 0) <= (others => '0');
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          rmask2(STAGE-1)          <= '0';
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          rmask2(STAGE-2 downto 0) <= (others => '1');
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        elsif signed(counter) = -1 then
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          rmask1 <= '0'&rmask1( STAGE-1 downto 1 );
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          rmask2 <= '0'&rmask2( STAGE-1 downto 1 );
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        end if;
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        aux_addrout     := counter2addr(counter, rmask1, rmask2);
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        aux_addrout_abs := abs(aux_addrout);
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        if unsigned(state) = 0 then
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          if mem_bk = '0' then
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            addrout_in <= aux_addrout_abs;
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          else
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            addrout_in <= aux_addrout_abs+32;
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          end if;
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        end if;
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        addrout_proc <= aux_addrout;
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      end if;
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    end process readaddr;
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  end generate;
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  Rx_read : if Tx_nRx = 0 generate
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    readaddr : process( clk, rst )
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      variable aux_addrout : std_logic_vector(stage*2 downto 0);
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    begin
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      if rst = '1' then
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        addrout_in   <= ( others => '0' );
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        addrout_proc <= ( others => '0' );
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        aux_addrout  := ( others => '0' );
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        rmask1       <= ( others => '0' );
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        rmask2       <= ( others => '0' );
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      elsif clk'event and clk = '1' then
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        if unsigned(state) = 0 and signed(counter) = 0 then
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          rmask1(STAGE-1)          <= '1';
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          rmask1(STAGE-2 downto 0) <= (others => '0');
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          rmask2(STAGE-1)          <= '0';
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          rmask2(STAGE-2 downto 0) <= (others => '1');
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        elsif signed(counter) = -1 then
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          rmask1 <= '0'&rmask1( STAGE-1 downto 1 );
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          rmask2 <= '0'&rmask2( STAGE-1 downto 1 );
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        end if;
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        aux_addrout := '0'&counter2addr(counter, rmask1, rmask2);
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        if unsigned(state) = 0 and mem_bk = '1' then
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          addrout_in <= aux_addrout+64;
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        else
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          addrout_in <= aux_addrout;
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        end if;
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        addrout_proc <= aux_addrout(stage*2-1 downto 0);
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      end if;
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    end process readaddr;
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  end generate;
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-- Escrita em proc
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  writeaddr_proc : process( clk, rst )
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  begin
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    if rst = '1' then
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      addrin_proc <= ( others => '0' );
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      wcounter    <= ( others => '0' );
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      wmask1      <= ( others => '0' );
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      wmask2      <= ( others => '0' );
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    elsif clk'event and clk = '1' then
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      if unsigned(state) = 0 and unsigned(counter) = FFTDELAY-1 then
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        wmask1(STAGE-1)          <= '1';
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        wmask1(STAGE-2 downto 0) <= (others => '0');
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        wmask2(STAGE-1)          <= '0';
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        wmask2(STAGE-2 downto 0) <= (others => '1');
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      elsif unsigned(counter) = FFTDELAY-1 then
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        wmask1 <= '0'&wmask1( STAGE-1 downto 1 );
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        wmask2 <= '0'&wmask2( STAGE-1 downto 1 );
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      end if;
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      if unsigned(state) < STAGE and unsigned(counter) = FFTDELAY-1 then
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        wcounter <= ( others => '0' );
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      else
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        wcounter <= unsigned(wcounter)+1;
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      end if;
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      addrin_proc <= counter2addr(wcounter, wmask1, wmask2 );
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    end if;
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  end process writeaddr_proc;
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  writeen_proc : process( clk, rst )
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  begin
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    if rst = '1' then
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      wen_proc <= '0';
174 
    elsif clk'event and clk = '1' then
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      if unsigned(state) = 0 and unsigned(counter) = FFTDELAY then
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        wen_proc <= '1';
177 
      elsif unsigned(state) = STAGE-1 and unsigned(counter) = FFTDELAY then
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        wen_proc <= '0';
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      end if;
180 
    end if;
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  end process writeen_proc;
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-- Escrite em OutRam
184 
 
185 
  writeaddr_out : process( clk, rst )
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  begin
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    if rst = '1' then
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      outcounter <= (others => '0');
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    elsif clk'event and clk = '1' then
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      if unsigned(state) = stage-1 and unsigned(counter) = OUTDELAY then
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        outcounter <= (others => '0');
192 
      else
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        outcounter <= unsigned(outcounter)+1;
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      end if;
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    end if;
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  end process writeaddr_out;
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  addrin_out <= outcounter2addr(outcounter);
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  writeen_out : process( clk, rst )
201 
  begin
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    if rst = '1' then
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      wen_out <= '0';
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    elsif clk'event and clk = '1' then
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      if unsigned(state) = STAGE-1 and unsigned(counter) = OUTDELAY then
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        wen_out <= '1';
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      elsif unsigned(outcounter) = 63 then
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        wen_out <= '0';
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      end if;
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    end if;
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  end process writeen_out;
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end ram_control;
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