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[/] [ofdm/] [branches/] [avendor/] [vhdl/] [inv_control.vhd] - Blame information for rev 13

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1 2 tmsiqueira
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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entity inv_control is
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  generic (
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    stage : natural:=3);
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  port (
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    clk       : in  std_logic;
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    rst       : in  std_logic;
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    Gen_state : in  std_logic_vector(2*stage+2 downto 0);
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    inv       : out std_logic);
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end inv_control;
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architecture inv_control of inv_control is
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  alias state   : std_logic_vector(2 downto 0) is Gen_state(2*stage+2 downto 2*stage);
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  alias counter : std_logic_vector(2*stage-1 downto 0) is Gen_state(2*stage-1 downto 0);
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begin
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  process (clk, rst)
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  begin  -- process
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    if rst = '1' then                   -- asynchronous reset (active low)
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      inv <= '0';
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    elsif clk'event and clk = '1' then  -- rising clock edge
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      if (unsigned(state) = 0) or (unsigned(state) = 1 and unsigned(counter)< 4) then
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        inv <= not(counter(1));
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      else
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                  inv <= '0';
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      end if;
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    end if;
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  end process;
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end inv_control;

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