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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity juntos is
  port(
    clk : in  std_logic;
    rst : in  std_logic;
    rx  : in  std_logic;
    tx  : out std_logic);
 
    end juntos;
 
    architecture Behavioral of juntos is
 
      component parallel
        port (
          clk    : in  std_logic;
          rst    : in  std_logic;
          input  : in  std_logic;
          output : out std_logic_vector(1 downto 0));
      end component;
 
      component qam
        port (
          clk   : in  std_logic;
          rst   : in  std_logic;
          input : in  std_logic_vector(1 downto 0);
          Iout  : out std_logic_vector(11 downto 0);
          Qout  : out std_logic_vector(11 downto 0));
      end component;
 
      component qamdecoder
        port (
          clk    : in  std_logic;
          rst    : in  std_logic;
          Iin    : in  std_logic_vector(11 downto 0);
          Qin    : in  std_logic_vector(11 downto 0);
          output : out std_logic_vector(1 downto 0));
      end component;
 
      component serial
        port (
          clk    : in  std_logic;
          rst    : in  std_logic;
          input  : in  std_logic_vector(1 downto 0);
          output : out std_logic);
      end component;
 
      signal input : std_logic_vector(1 downto 0);
      signal output : std_logic_vector(1 downto 0);
      signal Iin    :   std_logic_vector(11 downto 0);
      signal Qin    :   std_logic_vector(11 downto 0);
 
    begin
      par_input : parallel
        port map(
          clk    => clk,
          rst    => rst,
          input  => rx,
          output => input);
 
      qam_1 : qam
        port map (
          clk   => clk,
          rst   => rst,
          input => input,
          Iout  => Iin,
          Qout  => Qin);
 
 
      qamdecoder_1: qamdecoder
        port map (
          clk    => clk,
          rst    => rst,
          Iin    => Iin,
          Qin    => Qin,
          output => output);
 
      serial_1: serial
        port map (
          clk    => clk,
          rst    => rst,
          input  => output,
          output => tx);
 
    end Behavioral;

Line No.	Rev	Author	Line
1	2	tmsiqueira	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.all;`
3			`use IEEE.STD_LOGIC_ARITH.all;`
4			`use IEEE.STD_LOGIC_UNSIGNED.all;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`--library UNISIM;`
9			`--use UNISIM.VComponents.all;`
10
11			`entity juntos is`
12			`port(`
13			`clk : in std_logic;`
14			`rst : in std_logic;`
15			`rx : in std_logic;`
16			`tx : out std_logic);`
17
18			`end juntos;`
19
20			`architecture Behavioral of juntos is`
21
22			`component parallel`
23			`port (`
24			`clk : in std_logic;`
25			`rst : in std_logic;`
26			`input : in std_logic;`
27			`output : out std_logic_vector(1 downto 0));`
28			`end component;`
29
30			`component qam`
31			`port (`
32			`clk : in std_logic;`
33			`rst : in std_logic;`
34			`input : in std_logic_vector(1 downto 0);`
35			`Iout : out std_logic_vector(11 downto 0);`
36			`Qout : out std_logic_vector(11 downto 0));`
37			`end component;`
38
39			`component qamdecoder`
40			`port (`
41			`clk : in std_logic;`
42			`rst : in std_logic;`
43			`Iin : in std_logic_vector(11 downto 0);`
44			`Qin : in std_logic_vector(11 downto 0);`
45			`output : out std_logic_vector(1 downto 0));`
46			`end component;`
47
48			`component serial`
49			`port (`
50			`clk : in std_logic;`
51			`rst : in std_logic;`
52			`input : in std_logic_vector(1 downto 0);`
53			`output : out std_logic);`
54			`end component;`
55
56			`signal input : std_logic_vector(1 downto 0);`
57			`signal output : std_logic_vector(1 downto 0);`
58			`signal Iin : std_logic_vector(11 downto 0);`
59			`signal Qin : std_logic_vector(11 downto 0);`
60
61			`begin`
62			`par_input : parallel`
63			`port map(`
64			`clk => clk,`
65			`rst => rst,`
66			`input => rx,`
67			`output => input);`
68
69			`qam_1 : qam`
70			`port map (`
71			`clk => clk,`
72			`rst => rst,`
73			`input => input,`
74			`Iout => Iin,`
75			`Qout => Qin);`
76
77
78			`qamdecoder_1: qamdecoder`
79			`port map (`
80			`clk => clk,`
81			`rst => rst,`
82			`Iin => Iin,`
83			`Qin => Qin,`
84			`output => output);`
85
86			`serial_1: serial`
87			`port map (`
88			`clk => clk,`
89			`rst => rst,`
90			`input => output,`
91			`output => tx);`
92
93			`end Behavioral;`

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[/] [ofdm/] [branches/] [avendor/] [vhdl/] [juntos.vhd] - Blame information for rev 13