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[/] [ofdm/] [branches/] [avendor/] [vhdl/] [mulfactor.vhd] - Blame information for rev 13

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Line No. Rev Author Line
1 2 tmsiqueira
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--
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-- Title       : mulfactor
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-- Design      : cfft
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-- Author      : ZHAO Ming
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-- email           : sradio@opencores.org
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--
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---------------------------------------------------------------------------------------------------
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--
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-- File        : mulfactor.vhd
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-- Generated   : Thu Oct  3 00:37:40 2002
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Description : 360 degee complex rotation 
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Revisions       :    0
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-- Revision Number :    1
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-- Version         :    1.1.0
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-- Date            :    Oct 17 2002
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-- Modifier        :    ZHAO Ming 
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-- Desccription    :    Data width configurable 
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Revisions       :    0
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-- Revision Number :    2
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-- Version         :    1.2.1
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-- Date            :    Oct 18 2002
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-- Modifier        :    ZHAO Ming 
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-- Desccription    :    Point configurable      
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--
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---------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_SIGNED.all;
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entity mulfactor is
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        generic (
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                WIDTH : Natural:=12;
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                STAGE : Natural:=3
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        );
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         port(
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                 clk : in STD_LOGIC;
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                 rst : in STD_LOGIC;
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                 angle : in signed(2*STAGE-1 downto 0);
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                 I : in signed(WIDTH+1 downto 0);
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                 Q : in signed(WIDTH+1 downto 0);
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                 Iout : out signed(WIDTH+3 downto 0);
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                 Qout : out signed(WIDTH+3 downto 0)
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             );
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end mulfactor;
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architecture mulfactor of mulfactor is
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signal phase : signed( 2*STAGE-3 downto 0 );
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signal Xi,Yi : signed( WIDTH+1 downto 0 );
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component sc_corproc
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        generic(
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                WIDTH : Natural;
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                STAGE : Natural
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        );
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        port(
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                clk     : in std_logic;
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                ena     : in std_logic;
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                Xin     : in signed(WIDTH+1 downto 0);
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                Yin     : in signed(WIDTH+1 downto 0);
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                Ain : in signed(2*STAGE-3 downto 0 );
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                sin     : out signed(WIDTH+3 downto 0);
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                cos     : out signed(WIDTH+3 downto 0));
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end component;
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begin
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        u1: sc_corproc
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        generic map(
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                WIDTH=>WIDTH,
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                STAGE=>STAGE
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        )
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        port map (
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                clk=>clk,
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                ena=>'1',
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                Xin=>Xi,
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                Yin=>Yi,
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                Ain=>phase,
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                sin=>Qout,
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                cos=>Iout
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        );
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process( clk, rst )
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variable temp : std_logic_vector( 1 downto 0 );
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begin
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        if rst='1' then
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                phase<=( others=>'0' );
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                Xi<=( others=>'0' );
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                Yi<=( others=>'0' );
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        elsif clk'event and clk='1' then
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                phase<=angle( 2*STAGE-3 downto 0 );
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                temp:=std_logic_vector(angle( 2*STAGE-1 downto 2*STAGE-2 ));
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                case  temp is
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                        when "00" =>
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                        Xi<=I;
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                        Yi<=Q;
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                        when "01" =>
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                        Xi<=0-Q;
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                        Yi<=I;
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                        when "10" =>
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                        Xi<=0-I;
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                        Yi<=0-Q;
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                        when "11" =>
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                        Xi<=Q;
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                        Yi<=0-I;
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                        when others=>
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                        null;
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                end case;
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        end if;
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end process;
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end mulfactor;

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