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1 2 tmsiqueira
--
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--      VHDL implementation of cordic algorithm
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--
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-- File: p2r_cordic.vhd
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-- author: Richard Herveille
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-- rev. 1.0 initial release
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--
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--
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--
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-- This file is come from www.opencores.org
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-- 
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-- It has been modified by zhaom to enable 20 bit phase input
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Title       : p2r_cordic
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-- Design      : cfft
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--
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---------------------------------------------------------------------------------------------------
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--
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-- File        : p2r_cordic.vhd
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Description : Cordic arith pilepline 
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Revisions       :    0
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-- Revision Number :    1
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-- Version         :    1
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-- Date            :    Oct 17 2002
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-- Modifier        :    ZHAO Ming <sradio@opencores.org>
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-- Desccription    :    Data width configurable 
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--
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---------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity p2r_cordic is
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        generic(
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                PIPELINE : integer := 15;
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                WIDTH    : integer := 16);
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        port(
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                clk     : in std_logic;
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                ena : in std_logic;
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                Xi      : in signed(WIDTH -1 downto 0);
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                Yi : in signed(WIDTH -1 downto 0) := (others => '0');
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                Zi      : in signed(19 downto 0);
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                Xo      : out signed(WIDTH -1 downto 0);
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                Yo      : out signed(WIDTH -1 downto 0)
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        );
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end entity p2r_Cordic;
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architecture dataflow of p2r_cordic is
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        --
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        --      TYPE defenitions
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        --
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        type XYVector is array(PIPELINE downto 0) of signed(WIDTH -1 downto 0);
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        type ZVector is array(PIPELINE downto 0) of signed(19 downto 0);
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        --
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        --      COMPONENT declarations
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        --
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        component p2r_CordicPipe
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        generic(
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                WIDTH   : natural := 16;
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                PIPEID  : natural := 1
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        );
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        port(
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                clk             : in std_logic;
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                ena             : in std_logic;
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                Xi              : in signed(WIDTH -1 downto 0);
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                Yi              : in signed(WIDTH -1 downto 0);
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                Zi              : in signed(19 downto 0);
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                Xo              : out signed(WIDTH -1 downto 0);
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                Yo              : out signed(WIDTH -1 downto 0);
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                Zo              : out signed(19 downto 0)
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        );
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        end component p2r_CordicPipe;
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        --
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        --      SIGNALS
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        --
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        signal X, Y     : XYVector;
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        signal Z        : ZVector;
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        --
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        --      ACHITECTURE BODY
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        --
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begin
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        -- fill first nodes
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        -- fill X
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        X(0) <= Xi;
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        -- fill Y
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        Y(0) <= Yi;
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        -- fill Z
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        Z(0)(19 downto 0) <= Zi;                          -- modified by zhaom
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        --Z(0)(3 downto 0) <= (others => '0');  -- modified by zhaom
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        --
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        -- generate pipeline
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        --
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        gen_pipe:
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        for n in 1 to PIPELINE generate
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                Pipe: p2r_CordicPipe
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                        generic map(WIDTH => WIDTH, PIPEID => n -1)
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                        port map ( clk, ena, X(n-1), Y(n-1), Z(n-1), X(n), Y(n), Z(n) );
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        end generate gen_pipe;
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        --
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        -- assign outputs
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        --
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        Xo <= X(PIPELINE);
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        Yo <= Y(PIPELINE);
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end dataflow;
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