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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity txrx is
    Port ( clk : in std_logic;
           rst : in std_logic;
           Output_enable : in std_logic;
           mem_block : in std_logic;
           mem_ready : out std_logic;
           wen : out std_logic;
           address_read : out std_logic_vector(5 downto 0);
           address_write: out std_logic_vector(6 downto 0)
           );
end txrx;
 
architecture interface of txrx is
 
type state is (s0,s1,s2,s3);
signal st : state;
 
signal add : std_logic_vector(6 downto 0);
signal wen_aux : std_logic;
begin
 
address_read <= add(5 downto 0);
 
process(clk,rst)
begin
   if rst ='1' then
      address_write <= (others => '0');
      wen <= '0';
   elsif clk'event and clk='1' then
      address_write <= add;
      wen <= wen_aux;
   end if;
end process;
 
   process(clk,rst)
   begin
      if rst = '1' then
         add <= (others => '0');
         wen_aux <= '0';
         mem_ready <= '0';
      elsif clk'event and clk='1' then
         case st is
            when s0 => -- para contagem
               wen_aux <= '0';
               add <= add;
               mem_ready <= '0';
            when s1 => -- inicializa��o
               wen_aux <= '1';
               if mem_block = '1' then
                  add <= (others => '0');
               else
                  add <= conv_std_logic_vector(64,7);
               end if;
            when s2 => --contagem
               add <= add + 1;
            when s3 => --fim contagem
               add <= add + 1;
               mem_ready <= '1';
         end case;
      end if;
   end process;
 
   process(clk,rst)
   begin
      if rst = '1' then
         st <= s0;
      elsif clk'event and clk='1' then
         case st is
            when s0 => -- para contagem
               if Output_enable = '1' then
                  st <= s1;
               end if;
            when s1 => -- inicializa��o
               st <= s2;
            when s2 => -- contagem
               if (add(5 downto 0) = 61) then
                  st <= s3;
               end if;
            when s3 => -- fim contagem
               st <= s0;
         end case;
      end if;
   end process;
 
end interface;

Line No.	Rev	Author	Line
1	2	tmsiqueira	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`entity txrx is`
7			`Port ( clk : in std_logic;`
8			`rst : in std_logic;`
9			`Output_enable : in std_logic;`
10			`mem_block : in std_logic;`
11			`mem_ready : out std_logic;`
12			`wen : out std_logic;`
13			`address_read : out std_logic_vector(5 downto 0);`
14			`address_write: out std_logic_vector(6 downto 0)`
15			`);`
16			`end txrx;`
17
18			`architecture interface of txrx is`
19
20			`type state is (s0,s1,s2,s3);`
21			`signal st : state;`
22
23			`signal add : std_logic_vector(6 downto 0);`
24			`signal wen_aux : std_logic;`
25			`begin`
26
27			`address_read <= add(5 downto 0);`
28
29			`process(clk,rst)`
30			`begin`
31			`if rst ='1' then`
32			`address_write <= (others => '0');`
33			`wen <= '0';`
34			`elsif clk'event and clk='1' then`
35			`address_write <= add;`
36			`wen <= wen_aux;`
37			`end if;`
38			`end process;`
39
40			`process(clk,rst)`
41			`begin`
42			`if rst = '1' then`
43			`add <= (others => '0');`
44			`wen_aux <= '0';`
45			`mem_ready <= '0';`
46			`elsif clk'event and clk='1' then`
47			`case st is`
48			`when s0 => -- para contagem`
49			`wen_aux <= '0';`
50			`add <= add;`
51			`mem_ready <= '0';`
52			`when s1 => -- inicializa��o`
53			`wen_aux <= '1';`
54			`if mem_block = '1' then`
55			`add <= (others => '0');`
56			`else`
57			`add <= conv_std_logic_vector(64,7);`
58			`end if;`
59			`when s2 => --contagem`
60			`add <= add + 1;`
61			`when s3 => --fim contagem`
62			`add <= add + 1;`
63			`mem_ready <= '1';`
64			`end case;`
65			`end if;`
66			`end process;`
67
68			`process(clk,rst)`
69			`begin`
70			`if rst = '1' then`
71			`st <= s0;`
72			`elsif clk'event and clk='1' then`
73			`case st is`
74			`when s0 => -- para contagem`
75			`if Output_enable = '1' then`
76			`st <= s1;`
77			`end if;`
78			`when s1 => -- inicializa��o`
79			`st <= s2;`
80			`when s2 => -- contagem`
81			`if (add(5 downto 0) = 61) then`
82			`st <= s3;`
83			`end if;`
84			`when s3 => -- fim contagem`
85			`st <= s0;`
86			`end case;`
87			`end if;`
88			`end process;`
89
90	10	tmsiqueira	`end interface;`

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[/] [ofdm/] [branches/] [avendor/] [vhdl/] [txrx.vhd] - Blame information for rev 13