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URL https://opencores.org/ocsvn/ofdm/ofdm/trunk

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[/] [ofdm/] [trunk/] [vhdl/] [ofdm.vhd] - Blame information for rev 13

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1 2 tmsiqueira
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity ofdm is
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  generic (
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    Tx_nRx : natural := 1;
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    WIDTH : natural := 12;
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    POINT : natural := 64;
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    STAGE : natural := 3               -- STAGE=log4(POINT)
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    );
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  port (
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    clk       : in std_logic;
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    rst       : in std_logic;
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    mem_ready : in std_logic;
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    Iin  : in  std_logic_vector(WIDTH-1 downto 0);
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    Qin  : in  std_logic_vector(WIDTH-1 downto 0);
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    Iout : out std_logic_vector(WIDTH+1 downto 0);
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    Qout : out std_logic_vector(WIDTH+1 downto 0);
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    mem_block    : out std_logic;
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    Output_enable : out std_logic;
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    bank0_busy : out std_logic;
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    bank1_busy : out std_logic;
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    wen_in    : in std_logic;
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    addrin_in : in std_logic_vector(2*stage-Tx_nRX downto 0);
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    addrout_out : in std_logic_vector(2*stage-1 downto 0));
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end ofdm;
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architecture ofdm of ofdm is
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  component cfft_control
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    generic (
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      Tx_nRx : natural;
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      stage : natural);
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    port (
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      clk          : in  std_logic;
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      rst          : in  std_logic;
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      mem_ready    : in  std_logic;
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      sel_mux      : out std_logic;
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      factorstart  : out std_logic;
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      cfft4start   : out std_logic;
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      inv          : out std_logic;
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      Output_enable : out std_logic;
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      bank0_busy : out std_logic;
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      bank1_busy : out std_logic;
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      mem_block    : out std_logic;
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      addrout_in   : out std_logic_vector(stage*2-Tx_nRX downto 0);
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      wen_proc     : out std_logic;
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      addrin_proc  : out std_logic_vector(stage*2-1 downto 0);
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      addrout_proc : out std_logic_vector(stage*2-1 downto 0);
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      wen_out      : out std_logic;
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      addrin_out   : out std_logic_vector(stage*2-1 downto 0));
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  end component;
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  component cfft
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    generic (
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      Tx_nRx : natural;
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      WIDTH : natural;
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      POINT : natural;
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      STAGE : natural);
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    port (
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      rst          : in  std_logic;
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      Iin          : in  std_logic_vector(WIDTH-1 downto 0);
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      Qin          : in  std_logic_vector(WIDTH-1 downto 0);
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      Iout         : out std_logic_vector(WIDTH+1 downto 0);
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      Qout         : out std_logic_vector(WIDTH+1 downto 0);
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      factorstart  : in  std_logic;
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      cfft4start   : in  std_logic;
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      ClkIn        : in  std_logic;
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      sel_mux      : in  std_logic;
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      inv          : in  std_logic;
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      wen_in       : in  std_logic;
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      addrin_in    : in  std_logic_vector(2*stage-Tx_nRx downto 0);
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      addrout_in   : in  std_logic_vector(2*stage-Tx_nRx downto 0);
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      wen_proc     : in  std_logic;
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      addrin_proc  : in  std_logic_vector(2*stage-1 downto 0);
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      addrout_proc : in  std_logic_vector(2*stage-1 downto 0);
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      wen_out      : in  std_logic;
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      addrin_out   : in  std_logic_vector(2*stage-1 downto 0);
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      addrout_out  : in  std_logic_vector(2*stage-1 downto 0));
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  end component;
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  signal sel_mux      : std_logic;
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  signal factorstart  : std_logic;
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  signal cfft4start   : std_logic;
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  signal inv          : std_logic;
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  signal addrout_in   : std_logic_vector(stage*2-Tx_nRx downto 0);
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  signal wen_proc     : std_logic;
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  signal addrin_proc  : std_logic_vector(stage*2-1 downto 0);
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  signal addrout_proc : std_logic_vector(stage*2-1 downto 0);
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  signal wen_out      : std_logic;
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  signal addrin_out   : std_logic_vector(stage*2-1 downto 0);
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begin
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  cfft_control_1 : cfft_control
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    generic map (
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      Tx_nRx => Tx_nRx,
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      stage => stage)
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    port map (
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      clk          => clk,
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      rst          => rst,
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      mem_ready    => mem_ready,
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      sel_mux      => sel_mux,
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      factorstart  => factorstart,
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      cfft4start   => cfft4start,
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      inv          => inv,
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      Output_enable => Output_enable,
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                bank0_busy    => bank0_busy,
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                bank1_busy    => bank1_busy,
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      mem_block    => mem_block,
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      addrout_in   => addrout_in,
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      wen_proc     => wen_proc,
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      addrin_proc  => addrin_proc,
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      addrout_proc => addrout_proc,
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      wen_out      => wen_out,
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      addrin_out   => addrin_out);
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  cfft_1 : cfft
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    generic map (
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      Tx_nRx => Tx_nRx,
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      WIDTH => WIDTH,
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      POINT => POINT,
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      STAGE => STAGE)
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    port map (
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      rst          => rst,
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      Iin          => Iin,
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      Qin          => Qin,
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      Iout         => Iout,
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      Qout         => Qout,
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      factorstart  => factorstart,
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      cfft4start   => cfft4start,
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      ClkIn        => Clk,
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      sel_mux      => sel_mux,
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      inv          => inv,
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      wen_in       => wen_in,
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      addrin_in    => addrin_in,
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      addrout_in   => addrout_in,
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      wen_proc     => wen_proc,
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      addrin_proc  => addrin_proc,
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      addrout_proc => addrout_proc,
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      wen_out      => wen_out,
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      addrin_out   => addrin_out,
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      addrout_out  => addrout_out);
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end ofdm;

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