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[/] [ofdm/] [trunk/] [vhdl/] [rxmodem.vhd] - Blame information for rev 13

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1 2 tmsiqueira
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--  Uncomment the following lines to use the declarations that are
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--  provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity rxmodem is
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    Port ( clk : in std_logic;
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            rst : in std_logic;
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            mem_ready     : in  std_logic;
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            Iin           : in  std_logic_vector(11 downto 0);
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            mem_block     : out std_logic;
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            wen           : in  std_logic;
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            addrin_in     : in  std_logic_vector(6 downto 0);
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            txserial : out std_logic
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        );
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end rxmodem;
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architecture rxmodem of rxmodem is
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  component ofdm
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    generic (
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      Tx_nRx : natural;
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      WIDTH  : natural;
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      POINT  : natural;
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      STAGE  : natural);
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    port (
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      clk           : in  std_logic;
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      rst           : in  std_logic;
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      mem_ready     : in  std_logic;
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      Iin           : in  std_logic_vector(WIDTH-1 downto 0);
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      --Qin           : in  std_logic_vector(WIDTH-1 downto 0);
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      Iout          : out std_logic_vector(WIDTH+1 downto 0);
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      Qout          : out std_logic_vector(WIDTH+1 downto 0);
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      mem_block     : out std_logic;
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      Output_enable : out std_logic;
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      --bank0_busy    : out std_logic;
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      --bank1_busy    : out std_logic;
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      wen_in        : in  std_logic;
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      addrin_in     : in  std_logic_vector(2*stage-Tx_nRX downto 0);
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      addrout_out   : in  std_logic_vector(2*stage-1 downto 0));
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  end component;
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component output
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    Port ( clk : in std_logic;
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           rst : in std_logic;
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           Iout          : in std_logic_vector(13 downto 0);
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           Qout          : in std_logic_vector(13 downto 0);
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           Output_enable : in std_logic;
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           addrout_out   : out  std_logic_vector(5 downto 0);
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           txserial : out std_logic
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           );
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end component;
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signal Iout        : std_logic_vector(13 downto 0);
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signal Qout        : std_logic_vector(13 downto 0);
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signal Output_enable : std_logic;
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signal addrout_out : std_logic_vector(5 downto 0);
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begin
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  ofdm_1: ofdm
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    generic map (
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      Tx_nRx => 0,
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      WIDTH  => 12,
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      POINT  => 64,
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      STAGE  => 3)
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    port map (
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         clk           => clk,
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         rst           => rst,
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         mem_ready     => mem_ready,
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         Iin           => Iin,
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         --Qin           => (others => '0'),
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         Iout          => Iout,  --tratado
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         Qout          => Qout,  --tratado
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         mem_block     => mem_block,
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         Output_enable => Output_enable,  --tratado
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         wen_in        => wen,
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         addrin_in     => addrin_in,
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         addrout_out   => addrout_out);  --tratado
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 output_1: output
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    Port map (
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           clk           => clk          ,
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           rst           => rst          ,
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           Iout          => Iout         ,
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           Qout          => Qout         ,
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           Output_enable => Output_enable,
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           addrout_out   => addrout_out  ,
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           txserial      => txserial
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           );
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end rxmodem;

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