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[/] [ofdm/] [trunk/] [vhdl/] [sc_corproc.vhd] - Blame information for rev 13

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Line No. Rev Author Line
1 2 tmsiqueira
--
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-- This file is come from www.opencores.org
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--                                                                                 
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-- It has been modified by ZHAO Ming for 20 bit complex rotation
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Title       : sc_corproc
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-- Design      : cfft
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-- Author      : ZHAO Ming
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-- email           : sradio@opencores.org
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--
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---------------------------------------------------------------------------------------------------
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--
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-- File        : sc_corproc.vhd
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-- Generated   : Tue Jul 16 10:39:17 2002
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Description : complex rotation
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Revisions       :    0
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-- Revision Number :    1
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-- Version         :    1.1.0
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-- Date            :    Oct 17 2002
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-- Modifier        :    ZHAO Ming 
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-- Desccription    :    Data width configurable 
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Revisions       :    0
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-- Revision Number :    2
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-- Version         :    1.2.0
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-- Date            :    Oct 18 2002
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-- Modifier        :    ZHAO Ming 
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-- Desccription    :    Data width configurable 
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--
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---------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_signed.all;
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entity sc_corproc is
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        generic (
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                WIDTH : Natural;
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                STAGE : Natural
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        );
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        port(
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                clk     : in std_logic;
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                ena     : in std_logic;
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                Xin     : in signed(WIDTH+1 downto 0);
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                Yin     : in signed(WIDTH+1 downto 0);
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                Ain : in signed(2*STAGE-3 downto 0 );
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                sin     : out signed(WIDTH+3 downto 0);
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                cos     : out signed(WIDTH+3 downto 0)
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        );
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end entity sc_corproc;
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architecture dataflow of sc_corproc is
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        constant PipeLength : natural := 2*STAGE+2;
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        component p2r_cordic is
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        generic(
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                PIPELINE : integer := 15;
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                WIDTH    : integer := 16);
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        port(
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                clk : in std_logic;
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                ena : in std_logic;
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                Xi : in signed(WIDTH -1 downto 0);
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                Yi : in signed(WIDTH -1 downto 0) := (others => '0');
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                Zi : in signed(19 downto 0);
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                Xo : out signed(WIDTH -1 downto 0);
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                Yo : out signed(WIDTH -1 downto 0)
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        );
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        end component p2r_cordic;
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signal phase:signed( 19 downto 0 );
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signal Xi,Yi:signed( WIDTH+7 downto 0 );
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signal Xo,Yo:signed( WIDTH+7 downto 0 );
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signal zeros:signed( 19-STAGE*2 downto 0 );
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begin
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                Xi<= Xin(WIDTH+1)&Xin&"00000";
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                Yi<= Yin(WIDTH+1)&Yin&"00000";
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                zeros<=(others=>'0');
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                phase<="00"&Ain&zeros;
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                cos<=Xo(WIDTH+7)&Xo( WIDTH+7 downto 5 );
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                sin<=Yo(WIDTH+7)&Yo( WIDTH+7 downto 5 );
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        u1:     p2r_cordic
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                        generic map(PIPELINE => PipeLength, WIDTH => WIDTH+8)
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                        port map(clk => clk, ena => ena, Xi => Xi, Yi=>Yi,Zi => phase, Xo => Xo, Yo => Yo);
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end architecture dataflow;

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