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[/] [ofdm/] [trunk/] [vhdl/] [txrx.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity txrx is
    Port ( clk : in std_logic;
           rst : in std_logic;
           Output_enable : in std_logic;
           mem_block : in std_logic;
           mem_ready : out std_logic;
           wen : out std_logic;
           address_read : out std_logic_vector(5 downto 0);
           address_write: out std_logic_vector(6 downto 0)
           );
end txrx;
 
architecture interface of txrx is
 
type state is (s0,s1,s2,s3);
signal st : state;
 
signal add : std_logic_vector(6 downto 0);
signal wen_aux : std_logic;
begin
 
address_read <= add(5 downto 0);
 
process(clk,rst)
begin
   if rst ='1' then
      address_write <= (others => '0');
      wen <= '0';
   elsif clk'event and clk='1' then
      address_write <= add;
      wen <= wen_aux;
   end if;
end process;
 
   process(clk,rst)
   begin
      if rst = '1' then
         add <= (others => '0');
         wen_aux <= '0';
         mem_ready <= '0';
      elsif clk'event and clk='1' then
         case st is
            when s0 => -- para contagem
               wen_aux <= '0';
               add <= add;
               mem_ready <= '0';
            when s1 => -- inicializa��o
               wen_aux <= '1';
               if mem_block = '1' then
                  add <= (others => '0');
               else
                  add <= conv_std_logic_vector(64,7);
               end if;
            when s2 => --contagem
               add <= add + 1;
            when s3 => --fim contagem
               add <= add + 1;
               mem_ready <= '1';
         end case;
      end if;
   end process;
 
 
   process(clk,rst)
   begin
      if rst = '1' then
         st <= s0;
      elsif clk'event and clk='1' then
         case st is
            when s0 => -- para contagem
               if Output_enable = '1' then
                  st <= s1;
               end if;
            when s1 => -- inicializa��o
               st <= s2;
            when s2 => -- contagem
               if (add(5 downto 0) = 61) then
                  st <= s3;
               end if;
            when s3 => -- fim contagem
               st <= s0;
         end case;
      end if;
   end process;
 
end interface;

Line No.	Rev	Author	Line
1	2	tmsiqueira	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`-- Uncomment the following lines to use the declarations that are`
7			`-- provided for instantiating Xilinx primitive components.`
8			`--library UNISIM;`
9			`--use UNISIM.VComponents.all;`
10
11			`entity txrx is`
12			`Port ( clk : in std_logic;`
13			`rst : in std_logic;`
14			`Output_enable : in std_logic;`
15			`mem_block : in std_logic;`
16			`mem_ready : out std_logic;`
17			`wen : out std_logic;`
18			`address_read : out std_logic_vector(5 downto 0);`
19			`address_write: out std_logic_vector(6 downto 0)`
20			`);`
21			`end txrx;`
22
23			`architecture interface of txrx is`
24
25			`type state is (s0,s1,s2,s3);`
26			`signal st : state;`
27
28			`signal add : std_logic_vector(6 downto 0);`
29			`signal wen_aux : std_logic;`
30			`begin`
31
32			`address_read <= add(5 downto 0);`
33
34			`process(clk,rst)`
35			`begin`
36			`if rst ='1' then`
37			`address_write <= (others => '0');`
38			`wen <= '0';`
39			`elsif clk'event and clk='1' then`
40			`address_write <= add;`
41			`wen <= wen_aux;`
42			`end if;`
43			`end process;`
44
45			`process(clk,rst)`
46			`begin`
47			`if rst = '1' then`
48			`add <= (others => '0');`
49			`wen_aux <= '0';`
50			`mem_ready <= '0';`
51			`elsif clk'event and clk='1' then`
52			`case st is`
53			`when s0 => -- para contagem`
54			`wen_aux <= '0';`
55			`add <= add;`
56			`mem_ready <= '0';`
57			`when s1 => -- inicializa��o`
58			`wen_aux <= '1';`
59			`if mem_block = '1' then`
60			`add <= (others => '0');`
61			`else`
62			`add <= conv_std_logic_vector(64,7);`
63			`end if;`
64			`when s2 => --contagem`
65			`add <= add + 1;`
66			`when s3 => --fim contagem`
67			`add <= add + 1;`
68			`mem_ready <= '1';`
69			`end case;`
70			`end if;`
71			`end process;`
72
73
74			`process(clk,rst)`
75			`begin`
76			`if rst = '1' then`
77			`st <= s0;`
78			`elsif clk'event and clk='1' then`
79			`case st is`
80			`when s0 => -- para contagem`
81			`if Output_enable = '1' then`
82			`st <= s1;`
83			`end if;`
84			`when s1 => -- inicializa��o`
85			`st <= s2;`
86			`when s2 => -- contagem`
87			`if (add(5 downto 0) = 61) then`
88			`st <= s3;`
89			`end if;`
90			`when s3 => -- fim contagem`
91			`st <= s0;`
92			`end case;`
93			`end if;`
94			`end process;`
95
96			`end interface;`

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[/] [ofdm/] [trunk/] [vhdl/] [txrx.vhd] - Blame information for rev 2