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[/] [oks8/] [tags/] [v001/] [oks8sim.lst] - Blame information for rev 5

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Line No. Rev Author Line
1 5 kongzilee
 -------  FILE NO #1 : oks8sim.l -------
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Fri Jan 13 11:38:35 2006
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     SAM8 Assembler for Reduced Instruction  Ver. 2.10T(Win32)
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         Copyright (c) 1999 Samsung Electronics Co.
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    --------------------------------------------------------------------
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                       Source File Name : oks8sim.src
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                       Output File Name : oks8sim.o
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                       List File Name   : oks8sim.l
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    1                           .list   on
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    2
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    3                           .list on
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    4
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    5                    ;--------------<< Interrupt Vector Address >>
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    6  0000              .ORG 0000H
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    7
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    8  0000   01 51      .VECTOR 00H,INT_4208           ; KS86C4208 has only one interrupt vector
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    9
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   10  0100              .ORG 0100H
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   11
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   12  0100              INITIAL:
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   13
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   14  0100   E6 DF 00    LD SYM, #00H
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   15  0103   E6 DC A2    LD BTCON, #10100010B
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   16  0106   E6 D4 18    LD CLKCON, #00011000B ; non-divided CPU clock
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   17  0109   E6 D9 C0    LD SP, #0C0H                  ; 4208 -> 00~BF (After decrease, push data)
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   18                    ;--------------<< Port Initialization >>
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   19  010C   E6 E6 00    LD P0CONH, #0         ; input
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   20  010F   E6 E7 00    LD P0CONL, #0         ; input
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   21  0112   E6 E8 FF    LD P0PUR, #0FFH               ; pull-up enable
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   22  0115   E6 E9 50    LD P1CON, #50H                ; input, EXT.INT enable
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   23  0118   E6 EA F0    LD P1PND, #0F0H               ; pull-up enable
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   24  011B   E6 EB 00    LD P2CONH, #0         ; input
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   25  011E   E6 EC 00    LD P2CONL, #0         ; input
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   26  0121   E6 ED FF    LD P2PUR, #0FFH               ; pull-up enable
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   27  0124   E6 EE 00    LD P3CON, #0          ; push-pull output
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   28                    ;--------------<< Timer 0 Setting >>
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   29  0127   E6 D1 41    LD T0DATA, #41H               ; interrupt interval --1.667msec (10MHz base)
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   30  012A   E6 D3 42    LD T0CONL, #01000010B ; Timer 0 match output
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   31                    ;--------------<< RAM Area Clear >>
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   32  012D   0C 00       LD R0, #0             ; RAM clear area setting
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   33  012F               RAM_CLR:
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   34  012F   B1 C0       CLR @R0
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   35  0131   0E          INC R0
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   36  0132   A6 C0 BF    CP R0, #0BFH          ; general register area -> 00H~BFH
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   37                     ;JR ULE, RAM_CLR
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   38  0135   0B F8       JR F, RAM_CLR
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   39                    ;--------------<< Initialize Other Register >>
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   40                    ;,
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   41                    ;,
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   42                    ;,
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   43  0137   9F          EI
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   44
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   45                    ;--------------<< Main Loop >>
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   46  0138               MAIN:
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   47  0138   FF          NOP
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   48  0139   0C 33       LD R0, #33H
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   49                    ;,
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   50                    ;,
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   51                    ;,
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   52  013B   F6 01 44    CALL SUB_ROUTINE0     ; subroutine call
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   53                    ;,
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   54                    ;,
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   55                    ;,
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   56  013E   F6 01 4B    CALL SUB_ROUTINE1     ; subroutine call
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   57                    ;,
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   58                    ;,
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   59                    ;,
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   60  0141   8D 01 38    JP MAIN
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   61
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   62                    ;--------------<< Subroutine >>
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   63  0144              SUB_ROUTINE0:
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   64  0144   FF          NOP
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   65  0145   A7 00 04 11 LDC R0, 1104H
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   66                    ;,
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   67                    ;,
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   68                    ;,
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   69  0149   6F          IDLE
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   70  014A   AF          RET
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   71
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   72  014B              SUB_ROUTINE1:
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   73  014B   FF          NOP
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   74  014C   A7 01 04 11 LDE R0, 1104H
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   75                    ;,
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   76                    ;,
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   77                    ;,
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   78  0150   AF          RET
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   79
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   80                    ;--------------<< Interrupt Service Routine >>
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   81  0151              INT_4208:
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   82
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   83  0151   08 D3       LD R0, T0CONL         ; KS86C4208 has just one interrupt vector
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   84  0153   56 C0 03    AND R0, #00000011B    ; only Timer 0 match interrupt enable
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   85  0156   A6 C0 03    CP R0, #00000011B
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   86  0159   6D 01 5C    JP EQ, INT_TIMER0     ; T0CON¨s pending bit & INT. enable bit check
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   87  015C               INT_TIMER0:
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   88  015C   56 D3 FE    AND T0CONL, #11111110B        ; pending clear
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   89                    ;,
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   90                    ;,
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   91                    ;,
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   92  015F   A7 00 04 11 LDC R0, 1104H
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   93  0163   A7 01 04 11 LDE R0, 1104H
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   94  0167   A7 02 00 10 LDC R0, #1000H[RR2]
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   95  016B   A7 03 00 10 LDE R0, #1000H[RR2]
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   96  016F   E2 06       LDCD R0, @RR6
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   97  0171   E2 07       LDED R0, @RR6
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   98
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   99  0173   BF          IRET
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  100                    ;,
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  101                    ;,
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  102                    ;,
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  103
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Total 103 Lines Assembled - 0 Errors, 0 Warnings
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Total code size 0x76
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