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[/] [oks8/] [trunk/] [rtl/] [verilog/] [oks8_defines.v] - Blame information for rev 10

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//                              -*- Mode: Verilog -*-
// Filename        : oks8_defines.v
// Description     : OKS8 Defines
// Author          : Jian Li
// Created On      : Sat Jan 07 09:09:49 2006
// Last Modified By: .
// Last Modified On: .
// Update Count    : 0
// Status          : Unknown, Use with caution!
 
/*
 * Copyright (C) 2006 to Jian Li
 * Contact: kongzilee@yahoo.com.cn
 *
 * This source file may be used and distributed without restriction
 * provided that this copyright statement is not removed from the file
 * and that any derivative works contain the original copyright notice
 * and the associated disclaimer.
 *
 * THIS SOFTWARE IS PROVIDE "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
 * SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
 
`ifndef DEFINED
 
// =====================================================================
// EDITABLE/CONFIGURABLE DEFINES
// =====================================================================
 
//
// VENDOR for RAMS
// VENDOR_FPGA = Leave it to synthesis tool to decide
`define VENDOR_FPGA
 
// =====================================================================
// MISC DEFINES ** DO NOT EDIT **
// =====================================================================
`define DAT_Z           8'hZZ
 
// =====================================================================
// ALU Internal Operation Codes
// Selection mode for the correct ALU operations
// =====================================================================
`define ALU_AND         4'b0100         // AND/TM
`define ALU_IOR         4'b0101         // IOR
`define ALU_XOR         4'b0110         // XOR/COM(COM is XOR 0xFF)
`define ALU_TCM         4'b0111         // TCM
`define ALU_SRA         4'b0000         // SRA
`define ALU_LDCX        4'b0001         // LDCD(I)/LDED(I)
`define ALU_JP          4'b0010         // JP
`define ALU_NON         4'b0011         // NON
 
`define ALU_ADD         4'b1000         // ADD/DEC
`define ALU_ADC         4'b1001         // ADD+C
`define ALU_SUB         4'b1010         // SUB/INC
`define ALU_SBC         4'b1011         // SUB-C
`define ALU_RR          4'b1100         // RR
`define ALU_RRC         4'b1101         // RRC
`define ALU_RL          4'b1110         // RL
`define ALU_RLC         4'b1111         // RLC
 
// 
// SOURCE OPERAND SOURCE
// Used to indicate Source operand source
`define SRC_DA          3'b100          // DA
`define SRC_R           3'b101          // r/R
`define SRC_IR          3'b110          // ir/IR/x[r]
`define SRC_IRR         3'b111          // irr/IRR/XS[rr]/XL[rr]
`define SRC_IM          3'b000          // IM/NONE
`define SRC_RET         3'b001          // RET
`define SRC_POP         3'b010          // POP
`define SRC_IRET        3'b011          // IRET
 
// 
// DESTINATION OPERAND SOURCE
// Used to indicate destination operand source
`define DST_DA          3'b100          // DA
`define DST_R           3'b101          // r/R
`define DST_IR          3'b110          // ir/IR/x[r]
`define DST_IRR         3'b111          // irr/IRR/XS[rr]/XL[rr]
 
`define DST_NON         3'b000          // NONE/RA
`define DST_R2          3'b001          // R2
 
`define DST_PUSH        3'b010          // PUSH
`define DST_CALL        3'b011          // CALL
 
//
// STATUS AFFECTEd
// Used to indicate which Flags are affected
`define STS_NON         2'b00
`define STS_ZS0         2'b01
`define STS_ZSV         2'b10
`define STS_ALL         2'b11
 
// =====================================================================
// VECTORS ** DO NOT EDIT **
// Various Program and Data Address pointers.
// Also used to decode standard internal registers.
// =====================================================================
`define V_FLAGS         8'hD5
`define V_SP            8'hD9
`define V_SYM           8'hDF
`define V_RST           13'h0100
 
// =====================================================================
// WIDTH DEFINES ** DO NOT EDIT **
// =====================================================================
`define W_DATA          5'd8
`define W_INST          5'd13
 
// *** DEFINED ***
`define DEFINED
 
`endif

Line No.	Rev	Author	Line
1	7	kongzilee	`// -- Mode: Verilog --`
2			`// Filename : oks8_defines.v`
3			`// Description : OKS8 Defines`
4			`// Author : Jian Li`
5			`// Created On : Sat Jan 07 09:09:49 2006`
6			`// Last Modified By: .`
7			`// Last Modified On: .`
8			`// Update Count : 0`
9			`// Status : Unknown, Use with caution!`
10
11			`/*`
12			`* Copyright (C) 2006 to Jian Li`
13			`* Contact: kongzilee@yahoo.com.cn`
14			`*`
15			`* This source file may be used and distributed without restriction`
16			`* provided that this copyright statement is not removed from the file`
17			`* and that any derivative works contain the original copyright notice`
18			`* and the associated disclaimer.`
19			`*`
20			`* THIS SOFTWARE IS PROVIDE "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED`
21			`* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF`
22			`* MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT`
23			`* SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,`
24			`* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,`
25			`* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
26			`* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER`
27			`* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT`
28			`* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN`
29			`* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
30			`* POSSIBILITY OF SUCH DAMAGE.`
31			`*/`
32
33			`ifndef DEFINED
34
35			`// =====================================================================`
36			`// EDITABLE/CONFIGURABLE DEFINES`
37			`// =====================================================================`
38
39			`//`
40			`// VENDOR for RAMS`
41			`// VENDOR_FPGA = Leave it to synthesis tool to decide`
42			`define VENDOR_FPGA
43
44			`// =====================================================================`
45			`// MISC DEFINES DO NOT EDIT `
46			`// =====================================================================`
47			`define DAT_Z 8'hZZ
48
49			`// =====================================================================`
50			`// ALU Internal Operation Codes`
51			`// Selection mode for the correct ALU operations`
52			`// =====================================================================`
53			`define ALU_AND 4'b0100 // AND/TM
54			`define ALU_IOR 4'b0101 // IOR
55			`define ALU_XOR 4'b0110 // XOR/COM(COM is XOR 0xFF)
56			`define ALU_TCM 4'b0111 // TCM
57			`define ALU_SRA 4'b0000 // SRA
58			`define ALU_LDCX 4'b0001 // LDCD(I)/LDED(I)
59			`define ALU_JP 4'b0010 // JP
60			`define ALU_NON 4'b0011 // NON
61
62			`define ALU_ADD 4'b1000 // ADD/DEC
63			`define ALU_ADC 4'b1001 // ADD+C
64			`define ALU_SUB 4'b1010 // SUB/INC
65			`define ALU_SBC 4'b1011 // SUB-C
66			`define ALU_RR 4'b1100 // RR
67			`define ALU_RRC 4'b1101 // RRC
68			`define ALU_RL 4'b1110 // RL
69			`define ALU_RLC 4'b1111 // RLC
70
71			`//`
72			`// SOURCE OPERAND SOURCE`
73			`// Used to indicate Source operand source`
74			`define SRC_DA 3'b100 // DA
75			`define SRC_R 3'b101 // r/R
76			`define SRC_IR 3'b110 // ir/IR/x[r]
77			`define SRC_IRR 3'b111 // irr/IRR/XS[rr]/XL[rr]
78			`define SRC_IM 3'b000 // IM/NONE
79			`define SRC_RET 3'b001 // RET
80			`define SRC_POP 3'b010 // POP
81			`define SRC_IRET 3'b011 // IRET
82
83			`//`
84			`// DESTINATION OPERAND SOURCE`
85			`// Used to indicate destination operand source`
86			`define DST_DA 3'b100 // DA
87			`define DST_R 3'b101 // r/R
88			`define DST_IR 3'b110 // ir/IR/x[r]
89			`define DST_IRR 3'b111 // irr/IRR/XS[rr]/XL[rr]
90
91			`define DST_NON 3'b000 // NONE/RA
92			`define DST_R2 3'b001 // R2
93
94			`define DST_PUSH 3'b010 // PUSH
95			`define DST_CALL 3'b011 // CALL
96
97			`//`
98			`// STATUS AFFECTEd`
99			`// Used to indicate which Flags are affected`
100			`define STS_NON 2'b00
101			`define STS_ZS0 2'b01
102			`define STS_ZSV 2'b10
103			`define STS_ALL 2'b11
104
105			`// =====================================================================`
106			`// VECTORS DO NOT EDIT `
107			`// Various Program and Data Address pointers.`
108			`// Also used to decode standard internal registers.`
109			`// =====================================================================`
110			`define V_FLAGS 8'hD5
111			`define V_SP 8'hD9
112			`define V_SYM 8'hDF
113			`define V_RST 13'h0100
114
115			`// =====================================================================`
116			`// WIDTH DEFINES DO NOT EDIT `
117			`// =====================================================================`
118			`define W_DATA 5'd8
119			`define W_INST 5'd13
120
121			`// * DEFINED *`
122			`define DEFINED
123
124			`endif

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[/] [oks8/] [trunk/] [rtl/] [verilog/] [oks8_defines.v] - Blame information for rev 10