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//                              -*- Mode: Verilog -*-
// Filename        : oks8_execute.v
// Description     : OKS8 ALU and EXECUTION Unit
// Author          : Jian Li
// Created On      : Sat Jan 07 09:09:49 2006
// Last Modified By: .
// Last Modified On: .
// Update Count    : 0
// Status          : Unknown, Use with caution!
 
/*
 * Copyright (C) 2006 to Jian Li
 * Contact: kongzilee@yahoo.com.cn
 *
 * This source file may be used and distributed without restriction
 * provided that this copyright statement is not removed from the file
 * and that any derivative works contain the original copyright notice
 * and the associated disclaimer.
 *
 * THIS SOFTWARE IS PROVIDE "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
 * SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */
 
`include "oks8_defines.v"
`include "oks8_prims.v"
 
////////////////////////////////////////////////////
 
module oks8_execute (
  // Inputs
  clk_i, rst_i, en_i, int_i,
  dx_den, dx_alu, dx_sts, dx_r1_t, dx_r2_t, dx_r1, dx_r2, dx_r3, dat_i,
  // Outputs
  ex_final,
  ien_o, den_o, fen_o, we_o, add_o, dat_o
  );
 
// Inputs
input clk_i, rst_i;
input en_i, int_i;
input dx_den;
input [3:0] dx_alu;
input [1:0] dx_sts;
input [7:0] dx_r1;
input [2:0] dx_r1_t;
input [7:0] dx_r2;
input [2:0] dx_r2_t;
input [15:0] dx_r3;
input [7:0] dat_i;
 
// Outputs
output ex_final;
output [15:0] add_o;
output [7:0] dat_o;
output ien_o, den_o, fen_o, we_o;
 
// =====================================================================
// REGISTER/WIRE DECLARATIONS
// =====================================================================
// IMEM & DMEM & XMEM INTERFACE
reg fen_o, ien_o, den_o;
reg dwe_sp;
 
// Skipping/Jumping
reg [15:0] opc;
reg [15:0] dst_add;
wire skp_o, skp_t;
reg skp_old;
 
// SRC/DST
reg [7:0] src, dst;
wire [7:0] dat_dm;
wire ram_flags, ram_sp;
 
// INTERNAL REGISTERS & SHADOW
wire C_, Z_, S_, V_;
wire SV, CZ, ZSV;
reg C, Z, S, V;         // FLAGS
reg GIEN;                       // Global Interrupt Enable Bit
reg [1:0] PS;            // Page Selection Bits
reg [7:0] sp;            // Stack pointer
 
// ALU
wire [7:0] r_and, r_ior, r_xor, r_tcm;
wire [8:0] r_add, r_addc, r_sub, r_sbc;
wire [8:0] r_rr, r_rl, r_rrc, r_rlc, r_sra;
wire [8:0] res_;
 
wire [3:0]  alu;
wire [1:0]  sts;
wire [7:0]  r1;
wire [2:0]  r1_t;
wire [7:0]  r2;
wire [2:0]  r2_t;
wire [15:0] r3;
 
// INTERRUPT
reg [15:0] int_vec;
reg do_int_, int_, run_;
 
// FLAGS
reg [1:0] ex_state;
reg src_finish, dst_finish;
wire finish;
reg ex_final;
 
 
// ===============================================================
// INTERRUPT VECTOR
// The first thing I do after reset is to get the interrupt vector.
// ===============================================================
always @(posedge clk_i)
  if (rst_i) begin
        run_ <= 0;
        int_ <= 0;
        do_int_ <= 0;
        GIEN <= 0;
        PS <= 0;
        Z <= 0;
        S <= 0;
        V <= 0;
        C <= 0;
 
        ex_final <= 0;
        src_finish <= 0;
        dst_finish <= 0;
        do_int_ <= 0;
        ien_o <= 1'b0;
        fen_o <= 1'b0;
        den_o <= 1'b0;
        dwe_sp <= 0;
 
  end else if (!run_) begin
    case (ex_state)
          2'b00:
          begin
                ien_o <= 1'b1;
                dst_add[15:0] <= 16'h0000;
          end
          2'b01:
          begin
            int_vec[15:8] <= dat_dm[7:0];
                dst_add[15:0] <= 16'h0001;
          end
          2'b10:
          begin
            int_vec[7:0] <= dat_dm[7:0];
                src_finish <= 1;
                dst_finish <= 1;
                run_ <= 1;
          end
        endcase
  end
 
// ===============================================================
// ALU
// alu (or interrupt).
// ===============================================================
assign alu      = (en_i && do_int_) ? `ALU_NON : dx_alu;
assign sts      = (en_i && do_int_) ? `STS_NON : dx_sts;
assign r1_t     = (en_i && do_int_) ? `DST_CALL : dx_r1_t;
assign r1       = dx_r1;
assign r2_t = (en_i && do_int_) ? `SRC_DA : dx_r2_t;
assign r2       = dx_r2;
assign r3       = (en_i && do_int_) ? int_vec : dx_r3;
 
// ===============================================================
// ACTUAL DATA INPUT
// dat_i/flag/sp
// ===============================================================
assign dat_dm = (ram_flags) ? {C, Z, S, V, 4'h0} :
                (ram_sp) ? sp : dat_i;
 
// ===============================================================
// IMEM & DMEM INTERFACE
// ===============================================================
assign add_o = (en_i) ? ((ien_o | fen_o | den_o) ? dst_add[15:0] : opc) : 16'hZZZZ;
assign we_o = (en_i) && !(ex_final) && !(alu == `ALU_JP) && (finish ? (r1_t[2] | r1_t[1]): dwe_sp);
assign dat_o = (en_i) ? res_ : `DAT_Z;
 
// ===============================================================
// ACTUAL ALU
// Result selection
// ===============================================================
assign res_ = (alu == `ALU_AND) ? {C, r_and} :
        (alu == `ALU_IOR) ? {C, r_ior} :
        (alu == `ALU_XOR) ? {C, r_xor} :
        (alu == `ALU_TCM) ? {C, r_tcm} :
        (alu == `ALU_ADD) ? r_add :
        (alu == `ALU_ADC) ? r_addc :
        (alu == `ALU_SUB) ? r_sub :
        (alu == `ALU_SBC) ? r_sbc :
        (alu == `ALU_RR) ? r_rr :
        (alu == `ALU_RL) ? r_rl :
        (alu == `ALU_RRC) ? r_rrc :
        (alu == `ALU_RLC) ? r_rlc :
        (alu == `ALU_SRA) ? r_sra : {C, src};
 
oks8_and andU0(.a_i(dst), .b_i(src), .c_o(r_and));
oks8_ior iorU0(.a_i(dst), .b_i(src), .c_o(r_ior));
 
// oks8_xor xorU0(.a_i(dst), .b_i(src), .c_o(r_xor));
assign r_xor = r_tcm | (dst & ~(src));
oks8_tcm tcmU0(.a_i(dst), .b_i(src), .c_o(r_tcm));
 
oks8_add addU0(.a_i(dst), .b_i(src), .c_o(r_add));
oks8_adc addU1(.a_i(dst), .b_i(src), .c_i(C), .c_o(r_addc));
oks8_sub subU0(.a_i(dst), .b_i(src), .c_o(r_sub));
oks8_sbc subU1(.a_i(dst), .b_i(src), .c_i(~C), .c_o(r_sbc));
oks8_rr  rrU0(.a_i(dst), .c_o(r_rr));
oks8_rl  rlU0(.a_i(dst), .c_o(r_rl));
oks8_rrc rrcU0(.a_i({C,dst}), .c_o(r_rrc));
oks8_rlc rlcU0(.a_i({C,dst}), .c_o(r_rlc));
oks8_sra sraU0(.a_i(dst), .c_o(r_sra));
 
// ===============================================================
// STATUS
// Status effects/Skipping
// ===============================================================
 
assign C_ = (sts[1] && sts[0]) ? res_[8] : C;
assign Z_ = (sts[1] || sts[0]) ? (res_[7:0] == 8'h00) : Z;
assign S_ = (sts[1] || sts[0]) ? (res_[7]) : S;
assign V_ = (sts[1]) ? ((src[7] & dst[7] & !res_[7]) |
                        (~src[7] & ~dst[7] & res_[7])) : ((sts[0]) ? 0 : V);
 
assign SV = (S & ~V) | (~S & V);
assign ZSV = Z | SV;
assign CZ = C | Z;
 
assign skp_o = (en_i) && ((r1_t == `DST_CALL || r2_t == `SRC_RET ||
        r2_t == `SRC_IRET) ? 1'b1 : (alu == `ALU_JP) ? skp_t : 1'b0);
 
assign skp_t = (r2[2:0] == 3'b000) ? (r2[3]) : 1'bZ;
assign skp_t = (r2[2:0] == 3'b111) ? ((r2[3]) ? ~C : C) : 1'bZ;
assign skp_t = (r2[2:0] == 3'b110) ? ((r2[3]) ? ~Z : Z) : 1'bZ;
assign skp_t = (r2[2:0] == 3'b101) ? ((r2[3]) ? ~S : S) : 1'bZ;
assign skp_t = (r2[2:0] == 3'b100) ? ((r2[3]) ? ~V : V) : 1'bZ;
assign skp_t = (r2[2:0] == 3'b001) ? ((r2[3]) ? ~SV : SV) : 1'bZ;
assign skp_t = (r2[2:0] == 3'b010) ? ((r2[3]) ? ~ZSV : ZSV) : 1'bZ;
assign skp_t = (r2[2:0] == 3'b011) ? ((r2[3]) ? ~CZ : CZ) : 1'bZ;
 
// ===============================================================
// INTERNAL REGISTERS
// FLAG & SP & SYM
// ===============================================================
assign ram_flags = (fen_o && dst_add[7:0] == `V_FLAGS);
assign ram_sp = (fen_o && dst_add[7:0] == `V_SP);
 
always @(posedge clk_i)
begin
  if (finish) begin
        if (sts[1] && sts[0])
                C <= C_;
        if (sts[1] || sts[0]) begin
          Z <= Z_;
          S <= S_;
          V <= V_;
        end else begin
          if (dst_add[7:0] == `V_FLAGS)
                C <= res_[7];
          else if (dst_add[7:0] == `V_SP)
            sp <= res_[7:0];
          else if (dst_add[7:0] == `V_SYM)
                {GIEN, PS} <= res_[2:0];
        end
  end
end
 
 
// ===============================================================
// INTERRUPT
// Set interrupt flag
// ===============================================================
always @(posedge dst_finish)
  if (int_) begin
    do_int_ <= 1'b1;
        ex_state <= 2'b00;
  end
 
// ===============================================================
// JOB FINISH
// Exit normally without interrupt.
// ===============================================================
always @(posedge clk_i)
begin
  if (finish && !do_int_)
        begin
          if (!skp_o)
                dst_add <= opc;
          ien_o <= 1;
          fen_o <= 0;
          den_o <= 0;
          ex_final <= 1;
        end
end
 
// ===============================================================
// INITIALIZATION
// Do some cleanning when enter or exit
// ===============================================================
always @(posedge clk_i)
  if (rst_i)
        ex_state <= 0;
  else if (en_i)
        ex_state <= ex_state + 1'b1;
 
always @(en_i)
  if (en_i) begin
        opc <= add_o;
  end else
  begin
        ex_final <= 0;
        src_finish <= 0;
        dst_finish <= 0;
        ex_state <= 0;
        ien_o <= 0;
        dwe_sp <= 0;
  end
 
// ===============================================================
// MAIN JOBS
// Get/Set the SRC/DST
// ===============================================================
 
//
// Set when src & dst finish
//
assign finish = (en_i && src_finish && dst_finish);
 
//
// Get/Set the DST
//
always @(posedge src_finish)
begin
  if (int_i && GIEN) begin
        int_ <= 1;
        skp_old <= skp_o;
  end
  ex_state <= 2'b01;
  fen_o <= 1'b0;
  den_o <= 1'b0;
 
        case (r1_t)
          `DST_NON:
          begin
                if (alu == `ALU_JP)
                  dst_add[15:0] <= opc[15:0] + {r1[7], r1[7], r1[7], r1[7], r1[7], r1[7],
                                                                                r1[7], r1[7], r1[7:0]};
                dst_finish <= 1;
          end
          `DST_DA:
          begin
            den_o <= dx_den;
                ien_o <= ~dx_den;
                dst_add[15:0] <= r3[15:0];
                dst_finish <= 1;
          end
          `DST_R:
          begin
                fen_o <= 1'b1;
                dst_add[7:0] <= r1;
                if (alu == `ALU_NON)
                  dst_finish <= 1;
                else if (alu == `ALU_LDCX) begin
                  {dst_add[15:8], dst[7:0]} <= {dst_add[15:8], dst[7:0]} + r3[15:0];       // +1, -1
                  dwe_sp <= 1;
                end
          end
          `DST_R2, `DST_IR, `DST_IRR:
          begin
                fen_o <= 1'b1;
                dst_add[7:1] <= r1[7:1];
                if (dx_den)
                  dst_add[0] <= 1'b0;
                else
                  dst_add[0] <= r1[0];
          end
          `DST_PUSH:
          begin
                fen_o <= 1'b1;
                dwe_sp <= 1;
                dst_add[7:0] <= sp[7:0] + 8'hFF;
                sp <= sp + 8'hFF;
                dst_finish <= 1;
          end
          `DST_CALL:
          begin
                fen_o <= 1'b1;
                dwe_sp <= 1;
                dst_add[7:0] <= sp[7:0] + 8'hFF;
                src <= opc[7:0];
                sp <= sp + 8'hFF;
          end
          default:
          begin
                dst <= 8'hXX;
                dst_finish <= 1;
          end
        endcase // case (r1_t)
end     // always @(posedge src_finish)
 
always @(posedge clk_i)
begin
  if ((src_finish && !dst_finish) || (do_int_)) begin
    case (ex_state)
          2'b00:
          if (do_int_)
          begin
                fen_o <= 1'b1;
                dwe_sp <= 1;
                dst_add[7:0] <= sp[7:0] + 8'hFF;
                {dst_add[15:8], dst[7:0]} <= int_vec[15:0];
                if (!skp_old) begin
                  src <= opc[7:0];
                end else begin
                  src <= dst_add[7:0];
                  opc[15:8] <= dst_add[15:8];
                end
                sp <= sp + 8'hFF;
                GIEN <= 0;
          end
 
          2'b01:
                case (r1_t)
                  `DST_R2:
                  begin
                        dst <= dat_dm;
                        dst_finish <= 1;
                  end
                  `DST_R:
                  if (alu == `ALU_LDCX) begin
                        dst_add[7:0] <= r2[7:0];
                        src[7:0] <= dst_add[15:8];
                  end else begin
                        dst <= dat_dm;
                        dst_finish <= 1;
                  end
                  `DST_IR:
                  begin
                        dst_add[7:0] <= dat_dm + r3[7:0];
                    if (alu == `ALU_NON)
                          dst_finish <= 1;
                  end
                  `DST_IRR:
                  begin
                    dst_add[15:8] <= dat_dm[7:0];
                        if (dx_den)
                          dst_add[7:0] <= {r1[7:1], 1'b1};
                        else
                          dst_add[7:0] <= r1[7:0] + 1;
                  end
                  `DST_CALL:
                  begin
                        dst_add[7:0] <= sp[7:0] + 8'hFF;
                        src[7:0] <= opc[15:8];
                        sp <= sp + 8'hFF;
                  end
                endcase
          2'b10:
          begin
                case (r1_t)
                  `DST_R:
                        if (alu == `ALU_LDCX) begin
                          dst_add[7:0] <= r2[7:0] + 1'b1;
                          src[7:0] <= dst[7:0];
                          dst_finish <= 1;
                        end
                  `DST_CALL:
                        begin
                        if (do_int_) begin
                          dst_add[7:0] <= sp[7:0] + 8'hFF;
                          src[7:4] <= {C,Z,S,V};
                          sp <= sp + 8'hFF;
                        end else
                        begin
                          dst_add[7:0] = dst[7:0];
                          dst_finish <= 1;
                        end
                        end
                  `DST_IR:
                  begin
                        dst <= dat_dm;
                        dst_finish <= 1;
                  end
                  `DST_IRR:
                  begin
                        fen_o <= 1'b0;
                        if (dx_den) begin
                          den_o <= 1'b1;
                        end else begin
                          ien_o <= 1'b1;
                        end
                        dst_add[15:0] <= {dst_add[15:8], dat_dm} + r3[15:0];
                        dst_finish <= 1;
                  end
                endcase
          end
          2'b11:
          begin
                if (do_int_) begin
                  dst_add[7:0] = dst[7:0];
                  fen_o <= 0;
                  ien_o <= 1;
                  ex_final <= 1;
                  int_ <= 0;
                  do_int_ <= 0;
                end else begin
                  dst_finish <= 1;
                end
          end
        endcase // case (ex_state)
  end
end     // always @(posedge clk_i)
 
//
// Get/Set the SRC
//
always @(posedge clk_i)
begin
  if (en_i && run_ && (!src_finish))
  begin
    case (ex_state)
          2'b00:
                case (r2_t)
                  `SRC_DA:
                  if (r1_t == `DST_CALL) begin
                        {dst_add[15:8], dst[7:0]} <= r3[15:0];
                        src_finish <= 1;
                  end
                  else begin
                    den_o <= dx_den;
                        ien_o <= ~dx_den;
                        dst_add[15:0] <= r3[15:0];
                  end
                  `SRC_IM:
                  begin
                    src <= r2;
                        src_finish <= 1;
                  end
                  `SRC_R, `SRC_IR, `SRC_IRR:
                  begin
                    fen_o <= 1'b1;
                        dst_add[7:1] <= r2[7:1];
                        if (dx_den)
                          dst_add[0] <= 1'b0;
                        else
                          dst_add[0] <= r2[0];
                  end
                  `SRC_RET, `SRC_POP, `SRC_IRET:
                  begin
                    fen_o <= 1'b1;
                        dst_add[7:0] <= sp;
                        sp <= sp + 1'b1;
                  end
                  default:
                  begin
                        src <= 8'hXX;
                        src_finish <= 1;
                  end
                endcase
          2'b01:
                case (r2_t)
                  `SRC_DA, `SRC_R, `SRC_POP:
                  begin
                        src <= dat_dm;
                        ien_o <= 1'b0;
                        src_finish <= 1;
                  end
                  `SRC_IR:
                  begin
                        dst_add[7:0] <= dat_dm + r3[7:0];
                  end
                  `SRC_IRR:
                  begin
                        dst_add[15:8] <= dat_dm[7:0];
                        if (dx_den)
                          dst_add[7:0] <= {r2[7:1], 1'b1};
                        else
                          dst_add[7:0] <= r2[7:0] + 1'b1;
                  end
                  `SRC_RET:
                  begin
                        dst_add[15:8] <= dat_dm[7:0];
                        dst_add[7:0] <= sp;
                        sp <= sp + 1'b1;
                  end
                  `SRC_IRET:
                  begin
                        {C, Z, S, V} = dat_dm[7:4];
                        dst_add[7:0] <= sp;
                        sp <= sp + 1'b1;
                  end
                endcase
          2'b10:
                case (r2_t)
                  `SRC_IR:
                  begin
                        src <= dat_dm;
                        src_finish <= 1;
                  end
                  `SRC_IRR:
                  begin
                        fen_o <= 1'b0;
                        dst[7:0] <= dat_dm[7:0];
                        if (r1_t == `DST_CALL) begin
                          src_finish <= 1;
                        end
                        else begin
                          if (dx_den) begin
                                den_o <= 1'b1;
                          end else begin
                                ien_o <= 1'b1;
                          end
                          if (alu == `ALU_LDCX)
                                dst_add[7:0] <= dat_dm[7:0];
                          else
                                dst_add[15:0] <= {dst_add[15:8], dat_dm[7:0]} + r3[15:0];
                        end
                  end
                  `SRC_RET:
                  begin
                        dst_add[7:0] <= dat_dm;
                        src_finish <= 1;
                  end
                  `SRC_IRET:
                  begin
                        dst_add[15:8] <= dat_dm[7:0];
                        dst_add[7:0] <= sp;
                        sp <= sp + 1'b1;
                  end
                endcase
          2'b11:
          begin
                src_finish <= 1;
                case (r2_t)
                  `SRC_IRR:
                  begin
                        ien_o <= 1'b0;
                        src <= dat_dm;
                  end
                  `SRC_IRET:
                  begin
                        dst_add[7:0] <= dat_dm;
                        GIEN <= 1;
                  end
                endcase
          end
        endcase // case (ex_state)
  end
end     // always @(posedge clk_i)
 
endmodule       // oks8_execute

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[/] [oks8/] [trunk/] [rtl/] [verilog/] [oks8_execute.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	7	kongzilee	`// -- Mode: Verilog --`
2			`// Filename : oks8_execute.v`
3			`// Description : OKS8 ALU and EXECUTION Unit`
4			`// Author : Jian Li`
5			`// Created On : Sat Jan 07 09:09:49 2006`
6			`// Last Modified By: .`
7			`// Last Modified On: .`
8			`// Update Count : 0`
9			`// Status : Unknown, Use with caution!`
10
11			`/*`
12			`* Copyright (C) 2006 to Jian Li`
13			`* Contact: kongzilee@yahoo.com.cn`
14			`*`
15			`* This source file may be used and distributed without restriction`
16			`* provided that this copyright statement is not removed from the file`
17			`* and that any derivative works contain the original copyright notice`
18			`* and the associated disclaimer.`
19			`*`
20			`* THIS SOFTWARE IS PROVIDE "AS IS" AND WITHOUT ANY EXPRESS OR IMPLIED`
21			`* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF`
22			`* MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT`
23			`* SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,`
24			`* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,`
25			`* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
26			`* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER`
27			`* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT`
28			`* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN`
29			`* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
30			`* POSSIBILITY OF SUCH DAMAGE.`
31			`*/`
32
33			`include "oks8_defines.v"
34			`include "oks8_prims.v"
35
36			`////////////////////////////////////////////////////`
37
38			`module oks8_execute (`
39			`// Inputs`
40			`clk_i, rst_i, en_i, int_i,`
41			`dx_den, dx_alu, dx_sts, dx_r1_t, dx_r2_t, dx_r1, dx_r2, dx_r3, dat_i,`
42			`// Outputs`
43			`ex_final,`
44			`ien_o, den_o, fen_o, we_o, add_o, dat_o`
45			`);`
46
47			`// Inputs`
48			`input clk_i, rst_i;`
49			`input en_i, int_i;`
50			`input dx_den;`
51			`input [3:0] dx_alu;`
52			`input [1:0] dx_sts;`
53			`input [7:0] dx_r1;`
54			`input [2:0] dx_r1_t;`
55			`input [7:0] dx_r2;`
56			`input [2:0] dx_r2_t;`
57			`input [15:0] dx_r3;`
58			`input [7:0] dat_i;`
59
60			`// Outputs`
61			`output ex_final;`
62			`output [15:0] add_o;`
63			`output [7:0] dat_o;`
64			`output ien_o, den_o, fen_o, we_o;`
65
66			`// =====================================================================`
67			`// REGISTER/WIRE DECLARATIONS`
68			`// =====================================================================`
69			`// IMEM & DMEM & XMEM INTERFACE`
70			`reg fen_o, ien_o, den_o;`
71			`reg dwe_sp;`
72
73			`// Skipping/Jumping`
74			`reg [15:0] opc;`
75			`reg [15:0] dst_add;`
76			`wire skp_o, skp_t;`
77			`reg skp_old;`
78
79			`// SRC/DST`
80			`reg [7:0] src, dst;`
81			`wire [7:0] dat_dm;`
82			`wire ram_flags, ram_sp;`
83
84			`// INTERNAL REGISTERS & SHADOW`
85			`wire C_, Z_, S_, V_;`
86			`wire SV, CZ, ZSV;`
87			`reg C, Z, S, V; // FLAGS`
88			`reg GIEN; // Global Interrupt Enable Bit`
89			`reg [1:0] PS; // Page Selection Bits`
90			`reg [7:0] sp; // Stack pointer`
91
92			`// ALU`
93			`wire [7:0] r_and, r_ior, r_xor, r_tcm;`
94			`wire [8:0] r_add, r_addc, r_sub, r_sbc;`
95			`wire [8:0] r_rr, r_rl, r_rrc, r_rlc, r_sra;`
96			`wire [8:0] res_;`
97
98			`wire [3:0] alu;`
99			`wire [1:0] sts;`
100			`wire [7:0] r1;`
101			`wire [2:0] r1_t;`
102			`wire [7:0] r2;`
103			`wire [2:0] r2_t;`
104			`wire [15:0] r3;`
105
106			`// INTERRUPT`
107			`reg [15:0] int_vec;`
108			`reg do_int_, int_, run_;`
109
110			`// FLAGS`
111			`reg [1:0] ex_state;`
112			`reg src_finish, dst_finish;`
113			`wire finish;`
114			`reg ex_final;`
115
116
117			`// ===============================================================`
118			`// INTERRUPT VECTOR`
119			`// The first thing I do after reset is to get the interrupt vector.`
120			`// ===============================================================`
121			`always @(posedge clk_i)`
122			`if (rst_i) begin`
123			`run_ <= 0;`
124			`int_ <= 0;`
125			`do_int_ <= 0;`
126			`GIEN <= 0;`
127			`PS <= 0;`
128			`Z <= 0;`
129			`S <= 0;`
130			`V <= 0;`
131			`C <= 0;`
132
133			`ex_final <= 0;`
134			`src_finish <= 0;`
135			`dst_finish <= 0;`
136			`do_int_ <= 0;`
137			`ien_o <= 1'b0;`
138			`fen_o <= 1'b0;`
139			`den_o <= 1'b0;`
140			`dwe_sp <= 0;`
141
142			`end else if (!run_) begin`
143			`case (ex_state)`
144			`2'b00:`
145			`begin`
146			`ien_o <= 1'b1;`
147			`dst_add[15:0] <= 16'h0000;`
148			`end`
149			`2'b01:`
150			`begin`
151			`int_vec[15:8] <= dat_dm[7:0];`
152			`dst_add[15:0] <= 16'h0001;`
153			`end`
154			`2'b10:`
155			`begin`
156			`int_vec[7:0] <= dat_dm[7:0];`
157			`src_finish <= 1;`
158			`dst_finish <= 1;`
159			`run_ <= 1;`
160			`end`
161			`endcase`
162			`end`
163
164			`// ===============================================================`
165			`// ALU`
166			`// alu (or interrupt).`
167			`// ===============================================================`
168			assign alu = (en_i && do_int_) ? `ALU_NON : dx_alu;
169			assign sts = (en_i && do_int_) ? `STS_NON : dx_sts;
170			assign r1_t = (en_i && do_int_) ? `DST_CALL : dx_r1_t;
171			`assign r1 = dx_r1;`
172			assign r2_t = (en_i && do_int_) ? `SRC_DA : dx_r2_t;
173			`assign r2 = dx_r2;`
174			`assign r3 = (en_i && do_int_) ? int_vec : dx_r3;`
175
176			`// ===============================================================`
177			`// ACTUAL DATA INPUT`
178			`// dat_i/flag/sp`
179			`// ===============================================================`
180			`assign dat_dm = (ram_flags) ? {C, Z, S, V, 4'h0} :`
181			`(ram_sp) ? sp : dat_i;`
182
183			`// ===============================================================`
184			`// IMEM & DMEM INTERFACE`
185			`// ===============================================================`
186			`assign add_o = (en_i) ? ((ien_o \| fen_o \| den_o) ? dst_add[15:0] : opc) : 16'hZZZZ;`
187			assign we_o = (en_i) && !(ex_final) && !(alu == `ALU_JP) && (finish ? (r1_t[2] \| r1_t[1]): dwe_sp);
188			assign dat_o = (en_i) ? res_ : `DAT_Z;
189
190			`// ===============================================================`
191			`// ACTUAL ALU`
192			`// Result selection`
193			`// ===============================================================`
194			assign res_ = (alu == `ALU_AND) ? {C, r_and} :
195			(alu == `ALU_IOR) ? {C, r_ior} :
196			(alu == `ALU_XOR) ? {C, r_xor} :
197			(alu == `ALU_TCM) ? {C, r_tcm} :
198			(alu == `ALU_ADD) ? r_add :
199			(alu == `ALU_ADC) ? r_addc :
200			(alu == `ALU_SUB) ? r_sub :
201			(alu == `ALU_SBC) ? r_sbc :
202			(alu == `ALU_RR) ? r_rr :
203			(alu == `ALU_RL) ? r_rl :
204			(alu == `ALU_RRC) ? r_rrc :
205			(alu == `ALU_RLC) ? r_rlc :
206			(alu == `ALU_SRA) ? r_sra : {C, src};
207
208			`oks8_and andU0(.a_i(dst), .b_i(src), .c_o(r_and));`
209			`oks8_ior iorU0(.a_i(dst), .b_i(src), .c_o(r_ior));`
210
211			`// oks8_xor xorU0(.a_i(dst), .b_i(src), .c_o(r_xor));`
212			`assign r_xor = r_tcm \| (dst & ~(src));`
213			`oks8_tcm tcmU0(.a_i(dst), .b_i(src), .c_o(r_tcm));`
214
215			`oks8_add addU0(.a_i(dst), .b_i(src), .c_o(r_add));`
216			`oks8_adc addU1(.a_i(dst), .b_i(src), .c_i(C), .c_o(r_addc));`
217			`oks8_sub subU0(.a_i(dst), .b_i(src), .c_o(r_sub));`
218			`oks8_sbc subU1(.a_i(dst), .b_i(src), .c_i(~C), .c_o(r_sbc));`
219			`oks8_rr rrU0(.a_i(dst), .c_o(r_rr));`
220			`oks8_rl rlU0(.a_i(dst), .c_o(r_rl));`
221			`oks8_rrc rrcU0(.a_i({C,dst}), .c_o(r_rrc));`
222			`oks8_rlc rlcU0(.a_i({C,dst}), .c_o(r_rlc));`
223			`oks8_sra sraU0(.a_i(dst), .c_o(r_sra));`
224
225			`// ===============================================================`
226			`// STATUS`
227			`// Status effects/Skipping`
228			`// ===============================================================`
229
230			`assign C_ = (sts[1] && sts[0]) ? res_[8] : C;`
231			`assign Z_ = (sts[1] \|\| sts[0]) ? (res_[7:0] == 8'h00) : Z;`
232			`assign S_ = (sts[1] \|\| sts[0]) ? (res_[7]) : S;`
233			`assign V_ = (sts[1]) ? ((src[7] & dst[7] & !res_[7]) \|`
234			`(~src[7] & ~dst[7] & res_[7])) : ((sts[0]) ? 0 : V);`
235
236			`assign SV = (S & ~V) \| (~S & V);`
237			`assign ZSV = Z \| SV;`
238			`assign CZ = C \| Z;`
239
240			assign skp_o = (en_i) && ((r1_t == `DST_CALL \|\| r2_t == `SRC_RET \|\|
241			r2_t == `SRC_IRET) ? 1'b1 : (alu == `ALU_JP) ? skp_t : 1'b0);
242
243			`assign skp_t = (r2[2:0] == 3'b000) ? (r2[3]) : 1'bZ;`
244			`assign skp_t = (r2[2:0] == 3'b111) ? ((r2[3]) ? ~C : C) : 1'bZ;`
245			`assign skp_t = (r2[2:0] == 3'b110) ? ((r2[3]) ? ~Z : Z) : 1'bZ;`
246			`assign skp_t = (r2[2:0] == 3'b101) ? ((r2[3]) ? ~S : S) : 1'bZ;`
247			`assign skp_t = (r2[2:0] == 3'b100) ? ((r2[3]) ? ~V : V) : 1'bZ;`
248			`assign skp_t = (r2[2:0] == 3'b001) ? ((r2[3]) ? ~SV : SV) : 1'bZ;`
249			`assign skp_t = (r2[2:0] == 3'b010) ? ((r2[3]) ? ~ZSV : ZSV) : 1'bZ;`
250			`assign skp_t = (r2[2:0] == 3'b011) ? ((r2[3]) ? ~CZ : CZ) : 1'bZ;`
251
252			`// ===============================================================`
253			`// INTERNAL REGISTERS`
254			`// FLAG & SP & SYM`
255			`// ===============================================================`
256			assign ram_flags = (fen_o && dst_add[7:0] == `V_FLAGS);
257			assign ram_sp = (fen_o && dst_add[7:0] == `V_SP);
258
259			`always @(posedge clk_i)`
260			`begin`
261			`if (finish) begin`
262			`if (sts[1] && sts[0])`
263			`C <= C_;`
264			`if (sts[1] \|\| sts[0]) begin`
265			`Z <= Z_;`
266			`S <= S_;`
267			`V <= V_;`
268			`end else begin`
269			if (dst_add[7:0] == `V_FLAGS)
270			`C <= res_[7];`
271			else if (dst_add[7:0] == `V_SP)
272			`sp <= res_[7:0];`
273			else if (dst_add[7:0] == `V_SYM)
274			`{GIEN, PS} <= res_[2:0];`
275			`end`
276			`end`
277			`end`
278
279
280			`// ===============================================================`
281			`// INTERRUPT`
282			`// Set interrupt flag`
283			`// ===============================================================`
284			`always @(posedge dst_finish)`
285			`if (int_) begin`
286			`do_int_ <= 1'b1;`
287			`ex_state <= 2'b00;`
288			`end`
289
290			`// ===============================================================`
291			`// JOB FINISH`
292			`// Exit normally without interrupt.`
293			`// ===============================================================`
294			`always @(posedge clk_i)`
295			`begin`
296			`if (finish && !do_int_)`
297			`begin`
298			`if (!skp_o)`
299			`dst_add <= opc;`
300			`ien_o <= 1;`
301			`fen_o <= 0;`
302			`den_o <= 0;`
303			`ex_final <= 1;`
304			`end`
305			`end`
306
307			`// ===============================================================`
308			`// INITIALIZATION`
309			`// Do some cleanning when enter or exit`
310			`// ===============================================================`
311			`always @(posedge clk_i)`
312			`if (rst_i)`
313			`ex_state <= 0;`
314			`else if (en_i)`
315			`ex_state <= ex_state + 1'b1;`
316
317			`always @(en_i)`
318			`if (en_i) begin`
319			`opc <= add_o;`
320			`end else`
321			`begin`
322			`ex_final <= 0;`
323			`src_finish <= 0;`
324			`dst_finish <= 0;`
325			`ex_state <= 0;`
326			`ien_o <= 0;`
327			`dwe_sp <= 0;`
328			`end`
329
330			`// ===============================================================`
331			`// MAIN JOBS`
332			`// Get/Set the SRC/DST`
333			`// ===============================================================`
334
335			`//`
336			`// Set when src & dst finish`
337			`//`
338			`assign finish = (en_i && src_finish && dst_finish);`
339
340			`//`
341			`// Get/Set the DST`
342			`//`
343			`always @(posedge src_finish)`
344			`begin`
345			`if (int_i && GIEN) begin`
346			`int_ <= 1;`
347			`skp_old <= skp_o;`
348			`end`
349			`ex_state <= 2'b01;`
350			`fen_o <= 1'b0;`
351			`den_o <= 1'b0;`
352
353			`case (r1_t)`
354			`DST_NON:
355			`begin`
356			if (alu == `ALU_JP)
357			`dst_add[15:0] <= opc[15:0] + {r1[7], r1[7], r1[7], r1[7], r1[7], r1[7],`
358			`r1[7], r1[7], r1[7:0]};`
359			`dst_finish <= 1;`
360			`end`
361			`DST_DA:
362			`begin`
363			`den_o <= dx_den;`
364			`ien_o <= ~dx_den;`
365			`dst_add[15:0] <= r3[15:0];`
366			`dst_finish <= 1;`
367			`end`
368			`DST_R:
369			`begin`
370			`fen_o <= 1'b1;`
371			`dst_add[7:0] <= r1;`
372			if (alu == `ALU_NON)
373			`dst_finish <= 1;`
374			else if (alu == `ALU_LDCX) begin
375			`{dst_add[15:8], dst[7:0]} <= {dst_add[15:8], dst[7:0]} + r3[15:0]; // +1, -1`
376			`dwe_sp <= 1;`
377			`end`
378			`end`
379			`DST_R2, `DST_IR, `DST_IRR:
380			`begin`
381			`fen_o <= 1'b1;`
382			`dst_add[7:1] <= r1[7:1];`
383			`if (dx_den)`
384			`dst_add[0] <= 1'b0;`
385			`else`
386			`dst_add[0] <= r1[0];`
387			`end`
388			`DST_PUSH:
389			`begin`
390			`fen_o <= 1'b1;`
391			`dwe_sp <= 1;`
392			`dst_add[7:0] <= sp[7:0] + 8'hFF;`
393			`sp <= sp + 8'hFF;`
394			`dst_finish <= 1;`
395			`end`
396			`DST_CALL:
397			`begin`
398			`fen_o <= 1'b1;`
399			`dwe_sp <= 1;`
400			`dst_add[7:0] <= sp[7:0] + 8'hFF;`
401			`src <= opc[7:0];`
402			`sp <= sp + 8'hFF;`
403			`end`
404			`default:`
405			`begin`
406			`dst <= 8'hXX;`
407			`dst_finish <= 1;`
408			`end`
409			`endcase // case (r1_t)`
410			`end // always @(posedge src_finish)`
411
412			`always @(posedge clk_i)`
413			`begin`
414			`if ((src_finish && !dst_finish) \|\| (do_int_)) begin`
415			`case (ex_state)`
416			`2'b00:`
417			`if (do_int_)`
418			`begin`
419			`fen_o <= 1'b1;`
420			`dwe_sp <= 1;`
421			`dst_add[7:0] <= sp[7:0] + 8'hFF;`
422			`{dst_add[15:8], dst[7:0]} <= int_vec[15:0];`
423			`if (!skp_old) begin`
424			`src <= opc[7:0];`
425			`end else begin`
426			`src <= dst_add[7:0];`
427			`opc[15:8] <= dst_add[15:8];`
428			`end`
429			`sp <= sp + 8'hFF;`
430			`GIEN <= 0;`
431			`end`
432
433			`2'b01:`
434			`case (r1_t)`
435			`DST_R2:
436			`begin`
437			`dst <= dat_dm;`
438			`dst_finish <= 1;`
439			`end`
440			`DST_R:
441			if (alu == `ALU_LDCX) begin
442			`dst_add[7:0] <= r2[7:0];`
443			`src[7:0] <= dst_add[15:8];`
444			`end else begin`
445			`dst <= dat_dm;`
446			`dst_finish <= 1;`
447			`end`
448			`DST_IR:
449			`begin`
450			`dst_add[7:0] <= dat_dm + r3[7:0];`
451			if (alu == `ALU_NON)
452			`dst_finish <= 1;`
453			`end`
454			`DST_IRR:
455			`begin`
456			`dst_add[15:8] <= dat_dm[7:0];`
457			`if (dx_den)`
458			`dst_add[7:0] <= {r1[7:1], 1'b1};`
459			`else`
460			`dst_add[7:0] <= r1[7:0] + 1;`
461			`end`
462			`DST_CALL:
463			`begin`
464			`dst_add[7:0] <= sp[7:0] + 8'hFF;`
465			`src[7:0] <= opc[15:8];`
466			`sp <= sp + 8'hFF;`
467			`end`
468			`endcase`
469			`2'b10:`
470			`begin`
471			`case (r1_t)`
472			`DST_R:
473			if (alu == `ALU_LDCX) begin
474			`dst_add[7:0] <= r2[7:0] + 1'b1;`
475			`src[7:0] <= dst[7:0];`
476			`dst_finish <= 1;`
477			`end`
478			`DST_CALL:
479			`begin`
480			`if (do_int_) begin`
481			`dst_add[7:0] <= sp[7:0] + 8'hFF;`
482			`src[7:4] <= {C,Z,S,V};`
483			`sp <= sp + 8'hFF;`
484			`end else`
485			`begin`
486			`dst_add[7:0] = dst[7:0];`
487			`dst_finish <= 1;`
488			`end`
489			`end`
490			`DST_IR:
491			`begin`
492			`dst <= dat_dm;`
493			`dst_finish <= 1;`
494			`end`
495			`DST_IRR:
496			`begin`
497			`fen_o <= 1'b0;`
498			`if (dx_den) begin`
499			`den_o <= 1'b1;`
500			`end else begin`
501			`ien_o <= 1'b1;`
502			`end`
503			`dst_add[15:0] <= {dst_add[15:8], dat_dm} + r3[15:0];`
504			`dst_finish <= 1;`
505			`end`
506			`endcase`
507			`end`
508			`2'b11:`
509			`begin`
510			`if (do_int_) begin`
511			`dst_add[7:0] = dst[7:0];`
512			`fen_o <= 0;`
513			`ien_o <= 1;`
514			`ex_final <= 1;`
515			`int_ <= 0;`
516			`do_int_ <= 0;`
517			`end else begin`
518			`dst_finish <= 1;`
519			`end`
520			`end`
521			`endcase // case (ex_state)`
522			`end`
523			`end // always @(posedge clk_i)`
524
525			`//`
526			`// Get/Set the SRC`
527			`//`
528			`always @(posedge clk_i)`
529			`begin`
530			`if (en_i && run_ && (!src_finish))`
531			`begin`
532			`case (ex_state)`
533			`2'b00:`
534			`case (r2_t)`
535			`SRC_DA:
536			if (r1_t == `DST_CALL) begin
537			`{dst_add[15:8], dst[7:0]} <= r3[15:0];`
538			`src_finish <= 1;`
539			`end`
540			`else begin`
541			`den_o <= dx_den;`
542			`ien_o <= ~dx_den;`
543			`dst_add[15:0] <= r3[15:0];`
544			`end`
545			`SRC_IM:
546			`begin`
547			`src <= r2;`
548			`src_finish <= 1;`
549			`end`
550			`SRC_R, `SRC_IR, `SRC_IRR:
551			`begin`
552			`fen_o <= 1'b1;`
553			`dst_add[7:1] <= r2[7:1];`
554			`if (dx_den)`
555			`dst_add[0] <= 1'b0;`
556			`else`
557			`dst_add[0] <= r2[0];`
558			`end`
559			`SRC_RET, `SRC_POP, `SRC_IRET:
560			`begin`
561			`fen_o <= 1'b1;`
562			`dst_add[7:0] <= sp;`
563			`sp <= sp + 1'b1;`
564			`end`
565			`default:`
566			`begin`
567			`src <= 8'hXX;`
568			`src_finish <= 1;`
569			`end`
570			`endcase`
571			`2'b01:`
572			`case (r2_t)`
573			`SRC_DA, `SRC_R, `SRC_POP:
574			`begin`
575			`src <= dat_dm;`
576			`ien_o <= 1'b0;`
577			`src_finish <= 1;`
578			`end`
579			`SRC_IR:
580			`begin`
581			`dst_add[7:0] <= dat_dm + r3[7:0];`
582			`end`
583			`SRC_IRR:
584			`begin`
585			`dst_add[15:8] <= dat_dm[7:0];`
586			`if (dx_den)`
587			`dst_add[7:0] <= {r2[7:1], 1'b1};`
588			`else`
589			`dst_add[7:0] <= r2[7:0] + 1'b1;`
590			`end`
591			`SRC_RET:
592			`begin`
593			`dst_add[15:8] <= dat_dm[7:0];`
594			`dst_add[7:0] <= sp;`
595			`sp <= sp + 1'b1;`
596			`end`
597			`SRC_IRET:
598			`begin`
599			`{C, Z, S, V} = dat_dm[7:4];`
600			`dst_add[7:0] <= sp;`
601			`sp <= sp + 1'b1;`
602			`end`
603			`endcase`
604			`2'b10:`
605			`case (r2_t)`
606			`SRC_IR:
607			`begin`
608			`src <= dat_dm;`
609			`src_finish <= 1;`
610			`end`
611			`SRC_IRR:
612			`begin`
613			`fen_o <= 1'b0;`
614			`dst[7:0] <= dat_dm[7:0];`
615			if (r1_t == `DST_CALL) begin
616			`src_finish <= 1;`
617			`end`
618			`else begin`
619			`if (dx_den) begin`
620			`den_o <= 1'b1;`
621			`end else begin`
622			`ien_o <= 1'b1;`
623			`end`
624			if (alu == `ALU_LDCX)
625			`dst_add[7:0] <= dat_dm[7:0];`
626			`else`
627			`dst_add[15:0] <= {dst_add[15:8], dat_dm[7:0]} + r3[15:0];`
628			`end`
629			`end`
630			`SRC_RET:
631			`begin`
632			`dst_add[7:0] <= dat_dm;`
633			`src_finish <= 1;`
634			`end`
635			`SRC_IRET:
636			`begin`
637			`dst_add[15:8] <= dat_dm[7:0];`
638			`dst_add[7:0] <= sp;`
639			`sp <= sp + 1'b1;`
640			`end`
641			`endcase`
642			`2'b11:`
643			`begin`
644			`src_finish <= 1;`
645			`case (r2_t)`
646			`SRC_IRR:
647			`begin`
648			`ien_o <= 1'b0;`
649			`src <= dat_dm;`
650			`end`
651			`SRC_IRET:
652			`begin`
653			`dst_add[7:0] <= dat_dm;`
654			`GIEN <= 1;`
655			`end`
656			`endcase`
657			`end`
658			`endcase // case (ex_state)`
659			`end`
660			`end // always @(posedge clk_i)`
661
662			`endmodule // oks8_execute`