Subversion Repositories oms8051mini

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  8051 indirect address                                       ////

////                                                              ////

////  This file is part of the 8051 cores project                 ////

////  http://www.opencores.org/cores/oms8051mini/                 ////

////                                                              ////

////  Description                                                 ////

////   Contains ragister 0 and register 1. used for indirrect     ////

////   addressing.                                                ////

////                                                              ////

////  To Do:                                                      ////

////   nothing                                                    ////

////                                                              ////

////  Author(s):                                                  ////

////      - Simon Teran, simont@opencores.org                     ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////   v0.0 - Dinesh A, 5th Jan 2017

////        1. Active edge of reset changed from High to Low

////   v0.1 - Dinesh A, 19th Jan 2017

////        1. Lint warning fixes

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////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.6  2003/05/05 15:46:37  simont

// add aditional alu destination to solve critical path.

//

// Revision 1.5  2003/01/13 14:14:41  simont

// replace some modules

//

// Revision 1.4  2002/09/30 17:33:59  simont

// prepared header

//

//

module oc8051_indi_addr (clk, resetn, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);

//

input        clk,       // clock

             resetn,    // reset

             wr,        // write

             sel,       // select register

             wr_bit;    // write bit addressable

input  [1:0] bank;       // select register bank

input  [7:0] data_in;    // data input

input  [7:0] wr_addr;    // write address

output [7:0] ri_out;

//reg [7:0] buff [31:0];

reg wr_bit_r;

reg [7:0] buff [0:7];

//

//write to buffer

always @(posedge clk or negedge resetn)

begin

  if (resetn == 1'b0) begin

    buff[3'b000] <= #1 8'h00;

    buff[3'b001] <= #1 8'h00;

    buff[3'b010] <= #1 8'h00;

    buff[3'b011] <= #1 8'h00;

    buff[3'b100] <= #1 8'h00;

    buff[3'b101] <= #1 8'h00;

    buff[3'b110] <= #1 8'h00;

    buff[3'b111] <= #1 8'h00;

  end else begin

    if ((wr) & !(wr_bit_r)) begin

      case (wr_addr) /* synopsys full_case parallel_case */

        8'h00: buff[3'b000] <= #1 data_in;

        8'h01: buff[3'b001] <= #1 data_in;

        8'h08: buff[3'b010] <= #1 data_in;

        8'h09: buff[3'b011] <= #1 data_in;

        8'h10: buff[3'b100] <= #1 data_in;

        8'h11: buff[3'b101] <= #1 data_in;

        8'h18: buff[3'b110] <= #1 data_in;

        8'h19: buff[3'b111] <= #1 data_in;

        default : buff[3'b000] <= #1 data_in;

      endcase

    end

  end

end

//

//read from buffer

assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?

                 data_in : buff[{bank, sel}];

always @(posedge clk or negedge resetn)

  if (resetn == 1'b0) begin

    wr_bit_r <= #1 1'b0;

  end else begin

    wr_bit_r <= #1 wr_bit;

  end

endmodule