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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 memory interface                                       ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   comunication betwen cpu and memory                         ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
////   v0.1 - Dinesh A, 6th Jan 2017
////        1. pc_next logic added
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12  2003/07/01 20:47:39  simont
// add /* synopsys xx_case */ to case statments.
//
// Revision 1.11  2003/06/20 13:35:10  simont
// simualtion `ifdef added
//
// Revision 1.10  2003/06/05 11:15:02  simont
// fix bug.
//
// Revision 1.9  2003/06/03 17:09:57  simont
// pipelined acces to axternal instruction interface added.
//
// Revision 1.8  2003/05/12 16:27:40  simont
// fix bug in movc intruction.
//
// Revision 1.7  2003/05/06 09:39:34  simont
// cahnge assigment to pc_wait (remove istb_o)
//
// Revision 1.6  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.5  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.4  2003/04/16 10:04:09  simont
// chance idat_ir to 24 bit wide
//
// Revision 1.3  2003/04/11 10:05:08  simont
// Change pc add value from 23'h to 16'h
//
// Revision 1.2  2003/04/09 16:24:03  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.1  2003/01/13 14:13:12  simont
// initial import
//
//
 
 
`include "top_defines.v"
 
 
module oc8051_memory_interface (clk, resetn,
 
//decoder
     wr_i,
     wr_bit_i,
     rd_sel,
     wr_sel,
     pc_wr_sel,
     pc_wr,
     pc,
     pc_next,
     rd,
     mem_wait,
     mem_act,
     istb,
 
//internal ram
     wr_o,
     wr_bit_o,
     rd_addr,
     wr_addr,
     rd_ind,
     wr_ind,
     wr_dat,
 
     bit_in,
     in_ram,
     sfr,
     sfr_bit,
     bit_out,
     iram_out,
 
//program rom
     iadr_o,
     ea,
     ea_int,
     op1_out,
     op2_out,
     op3_out,
 
//internal
     idat_onchip,
 
//external
     iack_i,
     istb_o,
     idat_i,
 
//external data ram
     dadr_o,
     dwe_o,
     dstb_o,
     dack_i,
     ddat_i,
     ddat_o,
 
//interrupt interface
     intr,
     int_v,
     int_ack,
 
//alu
     des_acc,
     des1,
     des2,
 
//sfr's
     dptr,
     ri,
     sp,
     sp_w,
     rn,
     acc,
     reti
   );
 
 
input         clk,
              resetn,
              wr_i,
              wr_bit_i;
 
input         bit_in,
              sfr_bit,
              dack_i;
input [2:0]   mem_act;
input [7:0]   in_ram,
              sfr,
              acc,
              sp_w;
input [31:0]  idat_i;
 
output        bit_out,
              mem_wait,
              reti;
output [7:0]  iram_out,
              wr_dat;
 
reg           bit_out,
              reti;
reg [7:0]     iram_out,
              sp_r;
reg           rd_addr_r;
output        wr_o,
              wr_bit_o;
 
//????
reg           dack_ir;
reg [7:0]     ddat_ir;
reg [23:0]    idat_ir;
 
/////////////////////////////
//
//  rom_addr_sel
//
/////////////////////////////
input         iack_i;
input [7:0]   des_acc,
              des1,
              des2;
output [15:0] iadr_o;
 
wire          ea_rom_sel;
 
/////////////////////////////
//
// ext_addr_sel
//
/////////////////////////////
input [7:0]   ri,
              ddat_i;
input [15:0]  dptr;
 
output        dstb_o,
              dwe_o;
output [7:0]  ddat_o;
output [15:0] dadr_o;
 
/////////////////////////////
//
// ram_adr_sel
//
/////////////////////////////
 
input [2:0]   rd_sel,
              wr_sel;
input [4:0]   rn;
input [7:0]   sp;
 
output        rd_ind,
              wr_ind;
output [7:0]  wr_addr,
              rd_addr;
reg           rd_ind,
              wr_ind;
reg [7:0]     wr_addr,
              rd_addr;
 
reg [4:0]     rn_r;
reg [7:0]     ri_r,
              imm_r,
              imm2_r,
              op1_r;
wire [7:0]    imm,
              imm2;
 
/////////////////////////////
//
// op_select
//
/////////////////////////////
 
input         intr,
              rd,
              ea,
              ea_int,
              istb;
 
input  [7:0]  int_v;
 
input  [31:0] idat_onchip;
 
output        int_ack,
              istb_o;
 
output  [7:0] op1_out,
              op3_out,
              op2_out;
 
reg           int_ack_t,
              int_ack,
              int_ack_buff;
 
reg [7:0]     int_vec_buff;
reg [7:0]     op1_out,
              op2_buff,
              op3_buff;
reg [7:0]     op1_o,
              op2_o,
              op3_o;
 
reg [7:0]     op1_xt,
              op2_xt,
              op3_xt;
 
reg [7:0]     op1,
              op2,
              op3;
wire [7:0]    op2_direct;
 
input [2:0]   pc_wr_sel;
 
input         pc_wr;
output [15:0] pc;
output [15:0] pc_next;
 
reg [15:0]    pc,pc_next;
 
//
//pc            program counter register, save current value
reg [15:0]    pc_buf;
wire [15:0]   alu;
 
 
reg           int_buff,
              int_buff1; // interrupt buffer: used to prevent interrupting in the middle of executin instructions
 
 
//
//
////////////////////////////
reg           istb_t,
              imem_wait,
              dstb_o,
              dwe_o;
 
reg [7:0]     ddat_o;
reg [15:0]    iadr_t,
              dadr_ot;
reg           dmem_wait;
wire          pc_wait;
wire [1:0]    bank;
wire [7:0]    isr_call;
 
reg [1:0]     op_length;
reg [2:0]     op_pos;
wire          inc_pc;
 
reg           pc_wr_r;
 
wire [15:0]   pc_out;
 
reg [31:0]    idat_cur,
              idat_old;
 
reg           inc_pc_r,
              pc_wr_r2;
 
reg [7:0]     cdata;
reg           cdone;
 
 
assign bank       = rn[4:3];
assign imm        = op2_out;
assign imm2       = op3_out;
assign alu        = {des2, des_acc};
assign ea_rom_sel = ea && ea_int;
assign wr_o       = wr_i;
assign wr_bit_o   = wr_bit_i;
 
//assign mem_wait   = dmem_wait || imem_wait || pc_wr_r;
assign mem_wait   = dmem_wait || imem_wait || pc_wr_r2;
//assign mem_wait   = dmem_wait || imem_wait;
assign istb_o     = (istb || (istb_t & !iack_i)) && !dstb_o && !ea_rom_sel;
 
assign pc_wait    = rd && (ea_rom_sel || (!istb_t && iack_i));
 
assign wr_dat     = des1;
 
 
`ifdef OC8051_SIMULATION
  always @(negedge resetn) begin
    #5
    if (ea_rom_sel)
      $display("   progran execution from external rom");
    else
      $display("   progran execution from internal rom");
  end
 
`endif
 
 
/////////////////////////////
//
//  ram_select
//
/////////////////////////////
always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rd_ind)
begin
  if (rd_addr_r && !rd_ind) begin
    iram_out = sfr;
    bit_out = sfr_bit;
  end else begin
    iram_out = in_ram;
    bit_out = bit_in;
  end
end
 
/////////////////////////////
//
// ram_adr_sel
//
/////////////////////////////
 
always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank)
begin
  case (rd_sel) /* synopsys full_case parallel_case */
    `OC8051_RRS_RN   : rd_addr = {3'h0, rn};
    `OC8051_RRS_I    : rd_addr = ri;
    `OC8051_RRS_D    : rd_addr = imm;
    `OC8051_RRS_SP   : rd_addr = sp;
 
    `OC8051_RRS_B    : rd_addr = `OC8051_SFR_B;
    `OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
    `OC8051_RRS_PSW  : rd_addr = `OC8051_SFR_PSW;
    `OC8051_RRS_ACC  : rd_addr = `OC8051_SFR_ACC;
//    default          : rd_addr = 2'bxx;
  endcase
 
end
 
 
//
//
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
begin
  case (wr_sel) /* synopsys full_case parallel_case */
    `OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
    `OC8051_RWS_I  : wr_addr = ri_r;
    `OC8051_RWS_D  : wr_addr = imm_r;
    `OC8051_RWS_SP : wr_addr = sp_w;
    `OC8051_RWS_D3 : wr_addr = imm2_r;
    `OC8051_RWS_B  : wr_addr = `OC8051_SFR_B;
//    default        : wr_addr = 2'bxx;
  endcase
end
 
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0)
    rd_ind <= #1 1'b0;
  else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP))
    rd_ind <= #1 1'b1;
  else
    rd_ind <= #1 1'b0;
 
always @(wr_sel)
  if ((wr_sel==`OC8051_RWS_I) || (wr_sel==`OC8051_RWS_SP))
    wr_ind = 1'b1;
  else
    wr_ind = 1'b0;
 
 
/////////////////////////////
//
//  rom_addr_sel
//
/////////////////////////////
//
// output address is alu destination
// (instructions MOVC)
 
//assign iadr_o = (istb_t & !iack_i) ? iadr_t : pc_out;
assign iadr_o = (istb_t) ? iadr_t : pc_out;
 
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    iadr_t <= #1 23'h0;
    istb_t <= #1 1'b0;
    imem_wait <= #1 1'b0;
    idat_ir <= #1 24'h0;
  end else if (mem_act==`OC8051_MAS_CODE) begin
    iadr_t <= #1 alu;
    istb_t <= #1 1'b1;
    imem_wait <= #1 1'b1;
  end else if (ea_rom_sel && imem_wait) begin
    imem_wait <= #1 1'b0;
  end else if (!imem_wait && istb_t) begin
    istb_t <= #1 1'b0;
  end else if (iack_i) begin
    imem_wait <= #1 1'b0;
    idat_ir <= #1 idat_i [23:0];
  end
end
 
/////////////////////////////
//
// ext_addr_sel
//
/////////////////////////////
 
assign dadr_o = dadr_ot;
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    dwe_o <= #1 1'b0;
    dmem_wait <= #1 1'b0;
    dstb_o <= #1 1'b0;
    ddat_o <= #1 8'h00;
    dadr_ot <= #1 23'h0;
  end else if (dack_i) begin
    dwe_o <= #1 1'b0;
    dstb_o <= #1 1'b0;
    dmem_wait <= #1 1'b0;
  end else begin
    case (mem_act) /* synopsys full_case parallel_case */
      `OC8051_MAS_DPTR_R: begin  // read from external rom: acc=(dptr)
        dwe_o <= #1 1'b0;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 8'h00;
        dadr_ot <= #1 {7'h0, dptr};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_DPTR_W: begin  // write to external rom: (dptr)=acc
        dwe_o <= #1 1'b1;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 acc;
        dadr_ot <= #1 {7'h0, dptr};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_RI_R:   begin  // read from external rom: acc=(Ri)
        dwe_o <= #1 1'b0;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 8'h00;
        dadr_ot <= #1 {15'h0, ri};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_RI_W: begin    // write to external rom: (Ri)=acc
        dwe_o <= #1 1'b1;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 acc;
        dadr_ot <= #1 {15'h0, ri};
        dmem_wait <= #1 1'b1;
      end
    endcase
  end
end
 
/////////////////////////////
//
// op_select
//
/////////////////////////////
 
 
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    idat_cur <= #1 32'h0;
    idat_old <= #1 32'h0;
  end else if ((iack_i | ea_rom_sel) & (inc_pc | pc_wr_r2)) begin
    idat_cur <= #1 ea_rom_sel ? idat_onchip : idat_i;
    idat_old <= #1 idat_cur;
  end
 
end
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    cdata <= #1 8'h00;
    cdone <= #1 1'b0;
  end else if (istb_t) begin
    cdata <= #1 ea_rom_sel ? idat_onchip[7:0] : idat_i[7:0];
    cdone <= #1 1'b1;
  end else begin
    cdone <= #1 1'b0;
  end
end
 
always @(op_pos or idat_cur or idat_old)
begin
  case (op_pos)  /* synopsys parallel_case */
    3'b000: begin
       op1 = idat_old[7:0]  ;
       op2 = idat_old[15:8] ;
       op3 = idat_old[23:16];
      end
    3'b001: begin
       op1 = idat_old[15:8] ;
       op2 = idat_old[23:16];
       op3 = idat_old[31:24];
      end
    3'b010: begin
       op1 = idat_old[23:16];
       op2 = idat_old[31:24];
       op3 = idat_cur[7:0]  ;
      end
    3'b011: begin
       op1 = idat_old[31:24];
       op2 = idat_cur[7:0]  ;
       op3 = idat_cur[15:8] ;
      end
    3'b100: begin
       op1 = idat_cur[7:0]  ;
       op2 = idat_cur[15:8] ;
       op3 = idat_cur[23:16];
      end
    default: begin
       op1 = idat_cur[15:8] ;
       op2 = idat_cur[23:16];
       op3 = idat_cur[31:24];
      end
  endcase
end
 
 
always @(dack_ir or ddat_ir or op1_o or iram_out or cdone or cdata)
  if (dack_ir)
    op1_out = ddat_ir;
  else if (cdone)
    op1_out = cdata;
  else
    op1_out = op1_o;
 
assign op3_out = (rd) ? op3_o : op3_buff;
assign op2_out = (rd) ? op2_o : op2_buff;
 
always @(idat_i or iack_i or idat_ir or rd)
begin
  if (iack_i) begin
    op1_xt = idat_i[7:0];
    op2_xt = idat_i[15:8];
    op3_xt = idat_i[23:16];
  end else if (!rd) begin
    op1_xt = idat_ir[7:0];
    op2_xt = idat_ir[15:8];
    op3_xt = idat_ir[23:16];
  end else begin
    op1_xt = 8'h00;
    op2_xt = 8'h00;
    op3_xt = 8'h00;
  end
end
 
 
//
// in case of interrupts
always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)
begin
  if (int_ack_t && (iack_i || ea_rom_sel)) begin
    op1_o = `OC8051_LCALL;
    op2_o = 8'h00;
    op3_o = int_vec_buff;
  end else begin
    op1_o = op1;
    op2_o = op2;
    op3_o = op3;
  end
end
 
//
//in case of reti
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) reti <= #1 1'b0;
  else if ((op1_o==`OC8051_RETI) & rd & !mem_wait) reti <= #1 1'b1;
  else reti <= #1 1'b0;
 
//
// remember inputs
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    op2_buff <= #1 8'h0;
    op3_buff <= #1 8'h0;
  end else if (rd) begin
    op2_buff <= #1 op2_o;
    op3_buff <= #1 op3_o;
  end
end
 
/////////////////////////////
//
//  pc
//
/////////////////////////////
 
always @(op1_out)
begin
        casex (op1_out) /* synopsys parallel_case */
          `OC8051_ACALL :  op_length = 2'h2;
          `OC8051_AJMP :   op_length = 2'h2;
 
        //op_code [7:3]
          `OC8051_CJNE_R : op_length = 2'h3;
          `OC8051_DJNZ_R : op_length = 2'h2;
          `OC8051_MOV_DR : op_length = 2'h2;
          `OC8051_MOV_CR : op_length = 2'h2;
          `OC8051_MOV_RD : op_length = 2'h2;
 
        //op_code [7:1]
          `OC8051_CJNE_I : op_length = 2'h3;
          `OC8051_MOV_ID : op_length = 2'h2;
          `OC8051_MOV_DI : op_length = 2'h2;
          `OC8051_MOV_CI : op_length = 2'h2;
 
        //op_code [7:0]
          `OC8051_ADD_D :  op_length = 2'h2;
          `OC8051_ADD_C :  op_length = 2'h2;
          `OC8051_ADDC_D : op_length = 2'h2;
          `OC8051_ADDC_C : op_length = 2'h2;
          `OC8051_ANL_D :  op_length = 2'h2;
          `OC8051_ANL_C :  op_length = 2'h2;
          `OC8051_ANL_DD : op_length = 2'h2;
          `OC8051_ANL_DC : op_length = 2'h3;
          `OC8051_ANL_B :  op_length = 2'h2;
          `OC8051_ANL_NB : op_length = 2'h2;
          `OC8051_CJNE_D : op_length = 2'h3;
          `OC8051_CJNE_C : op_length = 2'h3;
          `OC8051_CLR_B :  op_length = 2'h2;
          `OC8051_CPL_B :  op_length = 2'h2;
          `OC8051_DEC_D :  op_length = 2'h2;
          `OC8051_DJNZ_D : op_length = 2'h3;
          `OC8051_INC_D :  op_length = 2'h2;
          `OC8051_JB :     op_length = 2'h3;
          `OC8051_JBC :    op_length = 2'h3;
          `OC8051_JC :     op_length = 2'h2;
          `OC8051_JNB :    op_length = 2'h3;
          `OC8051_JNC :    op_length = 2'h2;
          `OC8051_JNZ :    op_length = 2'h2;
          `OC8051_JZ :     op_length = 2'h2;
          `OC8051_LCALL :  op_length = 2'h3;
          `OC8051_LJMP :   op_length = 2'h3;
          `OC8051_MOV_D :  op_length = 2'h2;
          `OC8051_MOV_C :  op_length = 2'h2;
          `OC8051_MOV_DA : op_length = 2'h2;
          `OC8051_MOV_DD : op_length = 2'h3;
          `OC8051_MOV_CD : op_length = 2'h3;
          `OC8051_MOV_BC : op_length = 2'h2;
          `OC8051_MOV_CB : op_length = 2'h2;
          `OC8051_MOV_DP : op_length = 2'h3;
          `OC8051_ORL_D :  op_length = 2'h2;
          `OC8051_ORL_C :  op_length = 2'h2;
          `OC8051_ORL_AD : op_length = 2'h2;
          `OC8051_ORL_CD : op_length = 2'h3;
          `OC8051_ORL_B :  op_length = 2'h2;
          `OC8051_ORL_NB : op_length = 2'h2;
          `OC8051_POP :    op_length = 2'h2;
          `OC8051_PUSH :   op_length = 2'h2;
          `OC8051_SETB_B : op_length = 2'h2;
          `OC8051_SJMP :   op_length = 2'h2;
          `OC8051_SUBB_D : op_length = 2'h2;
          `OC8051_SUBB_C : op_length = 2'h2;
          `OC8051_XCH_D :  op_length = 2'h2;
          `OC8051_XRL_D :  op_length = 2'h2;
          `OC8051_XRL_C :  op_length = 2'h2;
          `OC8051_XRL_AD : op_length = 2'h2;
          `OC8051_XRL_CD : op_length = 2'h3;
          default:         op_length = 2'h1;
        endcase
end
 
 
assign inc_pc = ((op_pos[2] | (&op_pos[1:0])) & rd) | pc_wr_r2;
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    op_pos <= #1 3'h0;
  end else if (pc_wr_r2) begin
    op_pos <= #1 3'h4;// - op_length;////****??????????
  end else if (inc_pc & rd) begin
    op_pos[2]   <= #1 op_pos[2] & !op_pos[1] & op_pos[0] & (&op_length);
    op_pos[1:0] <= #1 op_pos[1:0] + op_length;
  end else if (rd) begin
    op_pos <= #1 op_pos + {1'b0, op_length};
  end
end
 
//
// remember interrupt
// we don't want to interrupt instruction in the middle of execution
always @(posedge clk or negedge resetn)
 if (resetn == 1'b0) begin
   int_ack_t <= #1 1'b0;
   int_vec_buff <= #1 8'h00;
 end else if (intr) begin
   int_ack_t <= #1 1'b1;
   int_vec_buff <= #1 int_v;
 end else if (rd && (ea_rom_sel || iack_i) && !pc_wr_r2) int_ack_t <= #1 1'b0;
 
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) int_ack_buff <= #1 1'b0;
  else int_ack_buff <= #1 int_ack_t;
 
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) int_ack <= #1 1'b0;
  else begin
    if ((int_ack_buff) & !(int_ack_t))
      int_ack <= #1 1'b1;
    else int_ack <= #1 1'b0;
  end
 
 
//
//interrupt buffer
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) begin
    int_buff1 <= #1 1'b0;
  end else begin
    int_buff1 <= #1 int_buff;
  end
 
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) begin
    int_buff <= #1 1'b0;
  end else if (intr) begin
    int_buff <= #1 1'b1;
  end else if (pc_wait)
    int_buff <= #1 1'b0;
 
wire [7:0]  pcs_source;
reg  [15:0] pcs_result;
reg         pcs_cy;
 
assign pcs_source = pc_wr_sel[0] ? op3_out : op2_out;
 
always @(pcs_source or pc or pcs_cy)
begin
  if (pcs_source[7]) begin
    {pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
    pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
  end else pcs_result = pc + {8'h00, pcs_source};
end
 
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0)
    pc <= #1 16'h0;
  else if (pc_wr_r2)
    pc <= #1 pc_buf;
  else if (rd && !int_ack_t && !(pc_wr && (pc_wr_sel != `OC8051_PIS_AH)) && !pc_wr_r)
    pc <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
end
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0)
    pc_next <= #1 16'h0;
  else if (pc_wr_r2)
    pc_next <= #1 pc_buf;
  else if (rd && !int_ack_t)
    pc_next <= #1 pc_buf - 16'h8 + {13'h0, op_pos} + {14'h0, op_length};
end
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    pc_buf <= #1 `OC8051_RST_PC;
  end else if (pc_wr) begin
//
//case of writing new value to pc (jupms)
      case (pc_wr_sel) /* synopsys full_case parallel_case */
        `OC8051_PIS_ALU: pc_buf        <= #1 alu;
        `OC8051_PIS_AL:  pc_buf[7:0]   <= #1 alu[7:0];
        `OC8051_PIS_AH:  pc_buf[15:8]  <= #1 alu[7:0];
        `OC8051_PIS_I11: pc_buf[10:0]  <= #1 {op1_out[7:5], op2_out};
        `OC8051_PIS_I16: pc_buf        <= #1 {op2_out, op3_out};
        `OC8051_PIS_SO1: pc_buf        <= #1 pcs_result;
        `OC8051_PIS_SO2: pc_buf        <= #1 pcs_result;
      endcase
//  end else if (inc_pc) begin
  end else begin
//
//or just remember current
      pc_buf <= #1 pc_out;
  end
end
 
 
assign pc_out = inc_pc ? pc_buf + 16'h4
                       : pc_buf ;
 
 
 
 
 
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0)
    ddat_ir <= #1 8'h00;
  else if (dack_i)
    ddat_ir <= #1 ddat_i;
 
 
////////////////////////
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) begin
    rn_r      <= #1 5'd0;
    ri_r      <= #1 8'h00;
    imm_r     <= #1 8'h00;
    imm2_r    <= #1 8'h00;
    rd_addr_r <= #1 1'b0;
    op1_r     <= #1 8'h0;
    dack_ir   <= #1 1'b0;
    sp_r      <= #1 1'b0;
    pc_wr_r   <= #1 1'b0;
    pc_wr_r2  <= #1 1'b0;
  end else begin
    rn_r      <= #1 rn;
    ri_r      <= #1 ri;
    imm_r     <= #1 imm;
    imm2_r    <= #1 imm2;
    rd_addr_r <= #1 rd_addr[7];
    op1_r     <= #1 op1_out;
    dack_ir   <= #1 dack_i;
    sp_r      <= #1 sp;
    pc_wr_r   <= #1 pc_wr && (pc_wr_sel != `OC8051_PIS_AH);
    pc_wr_r2  <= #1 pc_wr_r;
  end
 
always @(posedge clk or negedge resetn)
  if (resetn == 1'b0) begin
    inc_pc_r  <= #1 1'b1;
  end else if (istb) begin
    inc_pc_r  <= #1 inc_pc;
  end
 
`ifdef OC8051_SIMULATION
 
initial
begin
  wait (!resetn)
  if (ea_rom_sel) begin
    $display(" ");
    $display("\t Program running from internal rom !");
    $display(" ");
  end else begin
    $display(" ");
    $display("\t Program running from external rom !");
    $display(" ");
  end
end
`endif
 
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 memory interface ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// comunication betwen cpu and memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21	26	dinesha	`//// v0.1 - Dinesh A, 6th Jan 2017`
22			`//// 1. pc_next logic added`
23	25	dinesha	`//////////////////////////////////////////////////////////////////////`
24	2	dinesha	`//// ////`
25			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53			`// Revision 1.12 2003/07/01 20:47:39 simont`
54			`// add /* synopsys xx_case */ to case statments.`
55			`//`
56			`// Revision 1.11 2003/06/20 13:35:10 simont`
57			// simualtion `ifdef added
58			`//`
59			`// Revision 1.10 2003/06/05 11:15:02 simont`
60			`// fix bug.`
61			`//`
62			`// Revision 1.9 2003/06/03 17:09:57 simont`
63			`// pipelined acces to axternal instruction interface added.`
64			`//`
65			`// Revision 1.8 2003/05/12 16:27:40 simont`
66			`// fix bug in movc intruction.`
67			`//`
68			`// Revision 1.7 2003/05/06 09:39:34 simont`
69			`// cahnge assigment to pc_wait (remove istb_o)`
70			`//`
71			`// Revision 1.6 2003/05/05 15:46:37 simont`
72			`// add aditional alu destination to solve critical path.`
73			`//`
74			`// Revision 1.5 2003/04/25 17:15:51 simont`
75			`// change branch instruction execution (reduse needed clock periods).`
76			`//`
77			`// Revision 1.4 2003/04/16 10:04:09 simont`
78			`// chance idat_ir to 24 bit wide`
79			`//`
80			`// Revision 1.3 2003/04/11 10:05:08 simont`
81			`// Change pc add value from 23'h to 16'h`
82			`//`
83			`// Revision 1.2 2003/04/09 16:24:03 simont`
84			`// change wr_sft to 2 bit wire.`
85			`//`
86			`// Revision 1.1 2003/01/13 14:13:12 simont`
87			`// initial import`
88			`//`
89			`//`
90
91
92			`include "top_defines.v"
93
94
95	25	dinesha	`module oc8051_memory_interface (clk, resetn,`
96	2	dinesha
97			`//decoder`
98			`wr_i,`
99			`wr_bit_i,`
100			`rd_sel,`
101			`wr_sel,`
102			`pc_wr_sel,`
103			`pc_wr,`
104			`pc,`
105	26	dinesha	`pc_next,`
106	2	dinesha	`rd,`
107			`mem_wait,`
108			`mem_act,`
109			`istb,`
110
111			`//internal ram`
112			`wr_o,`
113			`wr_bit_o,`
114			`rd_addr,`
115			`wr_addr,`
116			`rd_ind,`
117			`wr_ind,`
118			`wr_dat,`
119
120			`bit_in,`
121			`in_ram,`
122			`sfr,`
123			`sfr_bit,`
124			`bit_out,`
125			`iram_out,`
126
127			`//program rom`
128			`iadr_o,`
129			`ea,`
130			`ea_int,`
131			`op1_out,`
132			`op2_out,`
133			`op3_out,`
134
135			`//internal`
136			`idat_onchip,`
137
138	20	dinesha	`//external`
139			`iack_i,`
140			`istb_o,`
141			`idat_i,`
142	2	dinesha
143			`//external data ram`
144			`dadr_o,`
145			`dwe_o,`
146			`dstb_o,`
147			`dack_i,`
148			`ddat_i,`
149			`ddat_o,`
150
151			`//interrupt interface`
152			`intr,`
153			`int_v,`
154			`int_ack,`
155
156			`//alu`
157			`des_acc,`
158			`des1,`
159			`des2,`
160
161			`//sfr's`
162			`dptr,`
163			`ri,`
164			`sp,`
165			`sp_w,`
166			`rn,`
167			`acc,`
168			`reti`
169			`);`
170
171
172			`input clk,`
173	25	dinesha	`resetn,`
174	2	dinesha	`wr_i,`
175			`wr_bit_i;`
176
177			`input bit_in,`
178			`sfr_bit,`
179			`dack_i;`
180			`input [2:0] mem_act;`
181			`input [7:0] in_ram,`
182			`sfr,`
183			`acc,`
184			`sp_w;`
185	20	dinesha	`input [31:0] idat_i;`
186	2	dinesha
187			`output bit_out,`
188			`mem_wait,`
189			`reti;`
190			`output [7:0] iram_out,`
191			`wr_dat;`
192
193			`reg bit_out,`
194			`reti;`
195			`reg [7:0] iram_out,`
196			`sp_r;`
197			`reg rd_addr_r;`
198			`output wr_o,`
199			`wr_bit_o;`
200
201			`//????`
202			`reg dack_ir;`
203			`reg [7:0] ddat_ir;`
204			`reg [23:0] idat_ir;`
205
206			`/////////////////////////////`
207			`//`
208			`// rom_addr_sel`
209			`//`
210			`/////////////////////////////`
211	20	dinesha	`input iack_i;`
212	2	dinesha	`input [7:0] des_acc,`
213			`des1,`
214			`des2;`
215			`output [15:0] iadr_o;`
216
217			`wire ea_rom_sel;`
218
219			`/////////////////////////////`
220			`//`
221			`// ext_addr_sel`
222			`//`
223			`/////////////////////////////`
224			`input [7:0] ri,`
225			`ddat_i;`
226			`input [15:0] dptr;`
227
228			`output dstb_o,`
229			`dwe_o;`
230			`output [7:0] ddat_o;`
231			`output [15:0] dadr_o;`
232
233			`/////////////////////////////`
234			`//`
235			`// ram_adr_sel`
236			`//`
237			`/////////////////////////////`
238
239			`input [2:0] rd_sel,`
240			`wr_sel;`
241			`input [4:0] rn;`
242			`input [7:0] sp;`
243
244			`output rd_ind,`
245			`wr_ind;`
246			`output [7:0] wr_addr,`
247			`rd_addr;`
248			`reg rd_ind,`
249			`wr_ind;`
250			`reg [7:0] wr_addr,`
251			`rd_addr;`
252
253			`reg [4:0] rn_r;`
254			`reg [7:0] ri_r,`
255			`imm_r,`
256			`imm2_r,`
257			`op1_r;`
258			`wire [7:0] imm,`
259			`imm2;`
260
261			`/////////////////////////////`
262			`//`
263			`// op_select`
264			`//`
265			`/////////////////////////////`
266
267			`input intr,`
268			`rd,`
269			`ea,`
270			`ea_int,`
271			`istb;`
272
273			`input [7:0] int_v;`
274
275			`input [31:0] idat_onchip;`
276
277	20	dinesha	`output int_ack,`
278			`istb_o;`
279	2	dinesha
280			`output [7:0] op1_out,`
281			`op3_out,`
282			`op2_out;`
283
284			`reg int_ack_t,`
285			`int_ack,`
286			`int_ack_buff;`
287
288			`reg [7:0] int_vec_buff;`
289			`reg [7:0] op1_out,`
290			`op2_buff,`
291			`op3_buff;`
292			`reg [7:0] op1_o,`
293			`op2_o,`
294			`op3_o;`
295
296			`reg [7:0] op1_xt,`
297			`op2_xt,`
298			`op3_xt;`
299
300			`reg [7:0] op1,`
301			`op2,`
302			`op3;`
303			`wire [7:0] op2_direct;`
304
305			`input [2:0] pc_wr_sel;`
306
307			`input pc_wr;`
308			`output [15:0] pc;`
309	26	dinesha	`output [15:0] pc_next;`
310	2	dinesha
311	26	dinesha	`reg [15:0] pc,pc_next;`
312	2	dinesha
313			`//`
314			`//pc program counter register, save current value`
315			`reg [15:0] pc_buf;`
316			`wire [15:0] alu;`
317
318
319			`reg int_buff,`
320			`int_buff1; // interrupt buffer: used to prevent interrupting in the middle of executin instructions`
321
322
323			`//`
324			`//`
325			`////////////////////////////`
326			`reg istb_t,`
327			`imem_wait,`
328			`dstb_o,`
329			`dwe_o;`
330
331			`reg [7:0] ddat_o;`
332			`reg [15:0] iadr_t,`
333			`dadr_ot;`
334			`reg dmem_wait;`
335			`wire pc_wait;`
336			`wire [1:0] bank;`
337			`wire [7:0] isr_call;`
338
339			`reg [1:0] op_length;`
340			`reg [2:0] op_pos;`
341			`wire inc_pc;`
342
343			`reg pc_wr_r;`
344
345			`wire [15:0] pc_out;`
346
347			`reg [31:0] idat_cur,`
348			`idat_old;`
349
350			`reg inc_pc_r,`
351			`pc_wr_r2;`
352
353			`reg [7:0] cdata;`
354			`reg cdone;`
355
356
357			`assign bank = rn[4:3];`
358			`assign imm = op2_out;`
359			`assign imm2 = op3_out;`
360			`assign alu = {des2, des_acc};`
361			`assign ea_rom_sel = ea && ea_int;`
362			`assign wr_o = wr_i;`
363			`assign wr_bit_o = wr_bit_i;`
364
365	20	dinesha	`//assign mem_wait = dmem_wait \|\| imem_wait \|\| pc_wr_r;`
366	2	dinesha	`assign mem_wait = dmem_wait \|\| imem_wait \|\| pc_wr_r2;`
367	20	dinesha	`//assign mem_wait = dmem_wait \|\| imem_wait;`
368			`assign istb_o = (istb \|\| (istb_t & !iack_i)) && !dstb_o && !ea_rom_sel;`
369	2	dinesha
370	20	dinesha	`assign pc_wait = rd && (ea_rom_sel \|\| (!istb_t && iack_i));`
371	2	dinesha
372			`assign wr_dat = des1;`
373
374
375			`ifdef OC8051_SIMULATION
376	25	dinesha	`always @(negedge resetn) begin`
377	2	dinesha	`#5`
378			`if (ea_rom_sel)`
379			`$display(" progran execution from external rom");`
380			`else`
381			`$display(" progran execution from internal rom");`
382			`end`
383
384			`endif
385
386
387			`/////////////////////////////`
388			`//`
389			`// ram_select`
390			`//`
391			`/////////////////////////////`
392			`always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rd_ind)`
393			`begin`
394			`if (rd_addr_r && !rd_ind) begin`
395			`iram_out = sfr;`
396			`bit_out = sfr_bit;`
397			`end else begin`
398			`iram_out = in_ram;`
399			`bit_out = bit_in;`
400			`end`
401			`end`
402
403			`/////////////////////////////`
404			`//`
405			`// ram_adr_sel`
406			`//`
407			`/////////////////////////////`
408
409	20	dinesha	`always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank)`
410	2	dinesha	`begin`
411			`case (rd_sel) /* synopsys full_case parallel_case */`
412			`OC8051_RRS_RN : rd_addr = {3'h0, rn};
413			`OC8051_RRS_I : rd_addr = ri;
414			`OC8051_RRS_D : rd_addr = imm;
415			`OC8051_RRS_SP : rd_addr = sp;
416
417			`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
418			`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
419			`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW;
420			`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC;
421	20	dinesha	`// default : rd_addr = 2'bxx;`
422	2	dinesha	`endcase`
423
424			`end`
425
426
427			`//`
428			`//`
429	20	dinesha	`always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])`
430	2	dinesha	`begin`
431			`case (wr_sel) /* synopsys full_case parallel_case */`
432			`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
433			`OC8051_RWS_I : wr_addr = ri_r;
434			`OC8051_RWS_D : wr_addr = imm_r;
435			`OC8051_RWS_SP : wr_addr = sp_w;
436			`OC8051_RWS_D3 : wr_addr = imm2_r;
437			`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
438			`// default : wr_addr = 2'bxx;`
439			`endcase`
440			`end`
441
442	25	dinesha	`always @(posedge clk or negedge resetn)`
443			`if (resetn == 1'b0)`
444	2	dinesha	`rd_ind <= #1 1'b0;`
445			else if ((rd_sel==`OC8051_RRS_I) \|\| (rd_sel==`OC8051_RRS_SP))
446			`rd_ind <= #1 1'b1;`
447			`else`
448			`rd_ind <= #1 1'b0;`
449
450			`always @(wr_sel)`
451			if ((wr_sel==`OC8051_RWS_I) \|\| (wr_sel==`OC8051_RWS_SP))
452			`wr_ind = 1'b1;`
453			`else`
454			`wr_ind = 1'b0;`
455
456
457			`/////////////////////////////`
458			`//`
459			`// rom_addr_sel`
460			`//`
461			`/////////////////////////////`
462			`//`
463			`// output address is alu destination`
464			`// (instructions MOVC)`
465
466	20	dinesha	`//assign iadr_o = (istb_t & !iack_i) ? iadr_t : pc_out;`
467	2	dinesha	`assign iadr_o = (istb_t) ? iadr_t : pc_out;`
468
469
470	25	dinesha	`always @(posedge clk or negedge resetn)`
471	2	dinesha	`begin`
472	25	dinesha	`if (resetn == 1'b0) begin`
473	2	dinesha	`iadr_t <= #1 23'h0;`
474			`istb_t <= #1 1'b0;`
475			`imem_wait <= #1 1'b0;`
476			`idat_ir <= #1 24'h0;`
477			end else if (mem_act==`OC8051_MAS_CODE) begin
478			`iadr_t <= #1 alu;`
479			`istb_t <= #1 1'b1;`
480			`imem_wait <= #1 1'b1;`
481			`end else if (ea_rom_sel && imem_wait) begin`
482			`imem_wait <= #1 1'b0;`
483			`end else if (!imem_wait && istb_t) begin`
484			`istb_t <= #1 1'b0;`
485	20	dinesha	`end else if (iack_i) begin`
486			`imem_wait <= #1 1'b0;`
487			`idat_ir <= #1 idat_i [23:0];`
488			`end`
489	2	dinesha	`end`
490
491			`/////////////////////////////`
492			`//`
493			`// ext_addr_sel`
494			`//`
495			`/////////////////////////////`
496
497			`assign dadr_o = dadr_ot;`
498
499	25	dinesha	`always @(posedge clk or negedge resetn)`
500	2	dinesha	`begin`

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