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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_64x32_dual_bist.v] - Blame information for rev 30

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cache ram                                              ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   64x31 dual port ram                                        ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
 
`include "top_defines.v"
 
//
// duble port ram
//
module oc8051_ram_64x32_dual_bist (
                     clk,
                     resetn,
 
                     adr0,
                     dat0_o,
                     en0,
 
                     adr1,
                     dat1_i,
                     dat1_o,
                     en1,
                     wr1
`ifdef OC8051_BIST
         ,
         scanb_rst,
         scanb_clk,
         scanb_si,
         scanb_so,
         scanb_en
`endif
                     );
 
parameter ADR_WIDTH = 6;
 
input         clk,
              wr1,
              resetn,
              en0,
              en1;
input  [7:0]  dat1_i;
input  [ADR_WIDTH-1:0]  adr0;
input  [ADR_WIDTH-1:0]  adr1;
 
output [31:0]  dat0_o;
output [31:0]  dat1_o;
 
reg    [7:0]  rd_data;
 
 
`ifdef OC8051_BIST
input   scanb_rst;
input   scanb_clk;
input   scanb_si;
output  scanb_so;
input   scanb_en;
`endif
 
 
`ifdef OC8051_RAM_XILINX
  xilinx_ram_dp u_ram_dp(
        // read port
        .CLKA(clk),
        .RSTA(resetn),
        .ENA(en0),
        .ADDRA(adr0),
        .DIA(32'h00),
        .WEA(1'b0),
        .DOA(dat0_o),
 
        // write port
        .CLKB(clk),
        .RSTB(resetn),
        .ENB(en1),
        .ADDRB(adr1),
        .DIB(dat1_i),
        .WEB(wr1),
        .DOB(dat1_o)
  );
 
  defparam
        xilinx_ram.dwidth = 32,
        xilinx_ram.awidth = ADR_WIDTH;
 
`else
 
  `ifdef OC8051_RAM_VIRTUALSILICON
 
  `else
 
    `ifdef OC8051_RAM_GENERIC
 
      generic_dpram #(ADR_WIDTH, 32) u_ram_dp(
        .rclk  ( clk            ),
        .resetn  ( resetn            ),
        .rce   ( en0            ),
        .oe    ( 1'b1           ),
        .raddr ( adr0           ),
        .do    ( dat0_o         ),
 
        .wclk  ( clk            ),
        .wresetn  ( resetn      ),
        .wce   ( en1            ),
        .we    ( wr1            ),
        .waddr ( adr1           ),
        .di    ( dat1_i         )
      );
 
    `else
 
      reg [31:0] dat1_o;
      reg [31:0] dat0_o;
      //
      // buffer
      reg    [31:0]  buff [0:(1<<ADR_WIDTH) -1];
 
      always @(posedge clk or negedge resetn)
      begin
        if (resetn == 1'b0)
          dat1_o     <= #1 32'h0;
        else if (wr1) begin
          buff[adr1] <= #1 dat1_i;
          dat1_o    <= #1 dat1_i;
        end else
          dat1_o <= #1 buff[adr1];
      end
 
      always @(posedge clk or negedge resetn)
      begin
        if (resetn == 1'b0)
          dat0_o <= #1 32'h0;
        else if ((adr0==adr1) & wr1)
          dat0_o <= #1 dat1_i;
        else
          dat0_o <= #1 buff[adr0];
      end
 
    `endif  //OC8051_RAM_GENERIC
  `endif    //OC8051_RAM_VIRTUALSILICON  
`endif      //OC8051_RAM_XILINX
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cache ram ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 64x31 dual port ram ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21			`//////////////////////////////////////////////////////////////////////`
22	2	dinesha	`//// ////`
23			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from http://www.opencores.org/lgpl.shtml ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47			`//`
48			`// CVS Revision History`
49			`//`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52			`//`
53
54
55			`include "top_defines.v"
56
57			`//`
58			`// duble port ram`
59			`//`
60			`module oc8051_ram_64x32_dual_bist (`
61			`clk,`
62	25	dinesha	`resetn,`
63	2	dinesha
64			`adr0,`
65			`dat0_o,`
66			`en0,`
67
68			`adr1,`
69			`dat1_i,`
70			`dat1_o,`
71			`en1,`
72			`wr1`
73			`ifdef OC8051_BIST
74			`,`
75			`scanb_rst,`
76			`scanb_clk,`
77			`scanb_si,`
78			`scanb_so,`
79			`scanb_en`
80			`endif
81			`);`
82
83			`parameter ADR_WIDTH = 6;`
84
85			`input clk,`
86			`wr1,`
87	25	dinesha	`resetn,`
88	2	dinesha	`en0,`
89			`en1;`
90			`input [7:0] dat1_i;`
91			`input [ADR_WIDTH-1:0] adr0;`
92			`input [ADR_WIDTH-1:0] adr1;`
93
94			`output [31:0] dat0_o;`
95			`output [31:0] dat1_o;`
96
97			`reg [7:0] rd_data;`
98
99
100			`ifdef OC8051_BIST
101			`input scanb_rst;`
102			`input scanb_clk;`
103			`input scanb_si;`
104			`output scanb_so;`
105			`input scanb_en;`
106			`endif
107
108
109			`ifdef OC8051_RAM_XILINX
110	20	dinesha	`xilinx_ram_dp u_ram_dp(`
111	2	dinesha	`// read port`
112			`.CLKA(clk),`
113	25	dinesha	`.RSTA(resetn),`
114	2	dinesha	`.ENA(en0),`
115			`.ADDRA(adr0),`
116			`.DIA(32'h00),`
117			`.WEA(1'b0),`
118			`.DOA(dat0_o),`
119
120			`// write port`
121			`.CLKB(clk),`
122	25	dinesha	`.RSTB(resetn),`
123	2	dinesha	`.ENB(en1),`
124			`.ADDRB(adr1),`
125			`.DIB(dat1_i),`
126			`.WEB(wr1),`
127			`.DOB(dat1_o)`
128			`);`
129
130			`defparam`
131			`xilinx_ram.dwidth = 32,`
132			`xilinx_ram.awidth = ADR_WIDTH;`
133
134			`else
135
136			`ifdef OC8051_RAM_VIRTUALSILICON
137
138			`else
139
140			`ifdef OC8051_RAM_GENERIC
141
142	20	dinesha	`generic_dpram #(ADR_WIDTH, 32) u_ram_dp(`
143	2	dinesha	`.rclk ( clk ),`
144	25	dinesha	`.resetn ( resetn ),`
145	2	dinesha	`.rce ( en0 ),`
146			`.oe ( 1'b1 ),`
147			`.raddr ( adr0 ),`
148			`.do ( dat0_o ),`
149
150			`.wclk ( clk ),`
151	25	dinesha	`.wresetn ( resetn ),`
152	2	dinesha	`.wce ( en1 ),`
153			`.we ( wr1 ),`
154			`.waddr ( adr1 ),`
155			`.di ( dat1_i )`
156			`);`
157
158			`else
159
160			`reg [31:0] dat1_o;`
161			`reg [31:0] dat0_o;`
162			`//`
163			`// buffer`
164			`reg [31:0] buff [0:(1<<ADR_WIDTH) -1];`
165
166	25	dinesha	`always @(posedge clk or negedge resetn)`
167	2	dinesha	`begin`
168	25	dinesha	`if (resetn == 1'b0)`
169	2	dinesha	`dat1_o <= #1 32'h0;`
170			`else if (wr1) begin`
171			`buff[adr1] <= #1 dat1_i;`
172			`dat1_o <= #1 dat1_i;`
173			`end else`
174			`dat1_o <= #1 buff[adr1];`
175			`end`
176
177	25	dinesha	`always @(posedge clk or negedge resetn)`
178	2	dinesha	`begin`
179	25	dinesha	`if (resetn == 1'b0)`
180	2	dinesha	`dat0_o <= #1 32'h0;`
181			`else if ((adr0==adr1) & wr1)`
182			`dat0_o <= #1 dat1_i;`
183			`else`
184			`dat0_o <= #1 buff[adr0];`
185			`end`
186
187			`endif //OC8051_RAM_GENERIC
188			`endif //OC8051_RAM_VIRTUALSILICON
189			`endif //OC8051_RAM_XILINX
190
191			`endmodule`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ram_64x32_dual_bist.v] - Blame information for rev 30