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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_sp.v] - Blame information for rev 26

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 stack pointer                                          ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   8051 special function register: stack pointer.             ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
////   v0.1 - Dinesh A, 6th Jan 2017
////        1. pc_next logic added
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.4  2002/11/05 17:23:54  simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.3  2002/09/30 17:33:59  simont
// prepared header
//
//
 
`include "top_defines.v"
 
 
 
module oc8051_sp (
                // General I/F
                  clk,
                  resetn,
 
                  ram_rd_sel,
                  ram_wr_sel,
 
                  // SP Reg Write I/F
                  wr_addr,
                  wr,
                  wr_bit,
                  data_in,
 
                  sp_out,
                  sp_w);
 
 
input clk, resetn, wr, wr_bit;
input [2:0] ram_rd_sel, ram_wr_sel;
input [7:0] data_in, wr_addr;
output [7:0] sp_out, sp_w;
 
reg [7:0] sp_out, sp_w;
reg pop;
wire write;
wire [7:0] sp_t;
 
reg [7:0] sp;
 
 
assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
 
assign sp_t= write ? data_in : sp;
 
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0)
    sp <= #1 `OC8051_RST_SP;
  else if (write)
    sp <= #1 data_in;
  else
    sp <= #1 sp_out;
end
 
 
always @(sp or ram_wr_sel)
begin
//
// push
  if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
  else sp_w = sp;
 
end
 
 
always @(sp_t or ram_wr_sel or pop or write)
begin
//
// push
  if (write) sp_out = sp_t;
  else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
  else sp_out = sp_t - {7'b0, pop};
 
end
 
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0)
    pop <= #1 1'b0;
  else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
  else pop <= #1 1'b0;
end
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 stack pointer ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 special function register: stack pointer. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21	26	dinesha	`//// v0.1 - Dinesh A, 6th Jan 2017`
22			`//// 1. pc_next logic added`
23	25	dinesha	`//////////////////////////////////////////////////////////////////////`
24	2	dinesha	`//// ////`
25			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53			`// Revision 1.5 2003/01/13 14:14:41 simont`
54			`// replace some modules`
55			`//`
56			`// Revision 1.4 2002/11/05 17:23:54 simont`
57			`// add module oc8051_sfr, 256 bytes internal ram`
58			`//`
59			`// Revision 1.3 2002/09/30 17:33:59 simont`
60			`// prepared header`
61			`//`
62			`//`
63
64			`include "top_defines.v"
65
66
67
68	26	dinesha	`module oc8051_sp (`
69			`// General I/F`
70			`clk,`
71			`resetn,`
72	2	dinesha
73	26	dinesha	`ram_rd_sel,`
74			`ram_wr_sel,`
75	2	dinesha
76	26	dinesha	`// SP Reg Write I/F`
77			`wr_addr,`
78			`wr,`
79			`wr_bit,`
80			`data_in,`
81
82			`sp_out,`
83			`sp_w);`
84
85
86	25	dinesha	`input clk, resetn, wr, wr_bit;`
87	2	dinesha	`input [2:0] ram_rd_sel, ram_wr_sel;`
88			`input [7:0] data_in, wr_addr;`
89			`output [7:0] sp_out, sp_w;`
90
91			`reg [7:0] sp_out, sp_w;`
92			`reg pop;`
93			`wire write;`
94			`wire [7:0] sp_t;`
95
96			`reg [7:0] sp;`
97
98
99			assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
100
101			`assign sp_t= write ? data_in : sp;`
102
103
104	25	dinesha	`always @(posedge clk or negedge resetn)`
105	2	dinesha	`begin`
106	25	dinesha	`if (resetn == 1'b0)`
107	2	dinesha	sp <= #1 `OC8051_RST_SP;
108			`else if (write)`
109			`sp <= #1 data_in;`
110			`else`
111			`sp <= #1 sp_out;`
112			`end`
113
114
115			`always @(sp or ram_wr_sel)`
116			`begin`
117			`//`
118			`// push`
119			if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
120			`else sp_w = sp;`
121
122			`end`
123
124
125			`always @(sp_t or ram_wr_sel or pop or write)`
126			`begin`
127			`//`
128			`// push`
129			`if (write) sp_out = sp_t;`
130			else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
131			`else sp_out = sp_t - {7'b0, pop};`
132
133			`end`
134
135
136	25	dinesha	`always @(posedge clk or negedge resetn)`
137	2	dinesha	`begin`
138	25	dinesha	`if (resetn == 1'b0)`
139	2	dinesha	`pop <= #1 1'b0;`
140			else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
141			`else pop <= #1 1'b0;`
142			`end`
143
144			`endmodule`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_sp.v] - Blame information for rev 26