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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores timer/counter2 control                           ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   timers and counters 2 8051 core                            ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2003/04/04 10:34:13  simont
// change timers to meet timing specifications (add divider with 12)
//
// Revision 1.1  2003/01/13 14:13:12  simont
// initial import
//
//
//
 
`include "top_defines.v"
 
 
 
module oc8051_tc2 (clk, resetn,
            wr_addr,
            data_in, bit_in,
            wr, wr_bit,
            t2, t2ex,
            rclk, tclk,
            brate2, tc2_int,
            pres_ow,
//registers
            t2con, tl2, th2, rcap2l, rcap2h);
 
input [7:0]  wr_addr,
             data_in;
input        clk,
             resetn,
             wr,
             wr_bit,
             t2,
             t2ex,
             bit_in,
             pres_ow;   //prescalre owerflov
output [7:0] t2con,
             tl2,
             th2,
             rcap2l,
             rcap2h;
output       tc2_int,
             rclk,
             tclk,
             brate2;
 
 
reg brate2;
reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;
 
reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;
 
wire run;
 
//
// t2con
wire tf2, exf2, exen2, tr2, ct2, cprl2;
 
assign tc2_int = tf2 | exf2;
assign tf2   = t2con[7];
assign exf2  = t2con[6];
assign rclk  = t2con[5];
assign tclk  = t2con[4];
assign exen2 = t2con[3];
assign tr2   = t2con[2];
assign ct2   = t2con[1];
assign cprl2 = t2con[0];
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    t2con <= `OC8051_RST_T2CON;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
    t2con <= data_in;
  end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
    t2con[wr_addr[2:0]] <= bit_in;
  end else if (tf2_set) begin
    t2con[7] <= 1'b1;
  end else if (exen2 & neg_trans) begin
    t2con[6] <= 1'b1;
  end
end
 
 
//
//th2, tl2
assign run = tr2 & ((!ct2 & pres_ow) | (ct2 & tc2_event));
 
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
//
// reset
//
    tl2 <= `OC8051_RST_TL2;
    th2 <= `OC8051_RST_TH2;
    brate2 <= 1'b0;
    tf2_set <= 1'b0;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin
//
// write to timer 2 high
//
    th2 <= data_in;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
//
// write to timer 2 low
//
    tl2 <= data_in;
  end else if (!(rclk | tclk) & !cprl2 & exen2 & neg_trans) begin
//
// avto reload mode, exen2=1, 0-1 transition on t2ex pin
//
    th2 <= rcap2h;
    tl2 <= rcap2l;
    tf2_set <= 1'b0;
  end else if (run) begin
    if (rclk | tclk) begin
//
// boud rate generator mode
//
      if (&{th2, tl2}) begin
        th2 <= rcap2h;
        tl2 <= rcap2l;
        brate2 <= 1'b1;
      end else begin
        {brate2, th2, tl2}  <= {1'b0, th2, tl2} + 17'h1;
      end
      tf2_set <= 1'b0;
    end else if (cprl2) begin
//
// capture mode
//
      {tf2_set, th2, tl2}  <= {1'b0, th2, tl2} + 17'h1;
    end else begin
//
// auto reload mode
//
      if (&{th2, tl2}) begin
        th2 <= rcap2h;
        tl2 <= rcap2l;
        tf2_set <= 1'b1;
      end else begin
        {tf2_set, th2, tl2} <= {1'b0, th2, tl2} + 17'h1;
      end
    end
  end else tf2_set <= 1'b0;
end
 
 
//
// rcap2l, rcap2h
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    rcap2l <= `OC8051_RST_RCAP2L;
    rcap2h <= `OC8051_RST_RCAP2H;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
    rcap2h <= data_in;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
    rcap2l <= data_in;
  end else if (!(rclk | tclk) & exen2 & cprl2 & neg_trans) begin
    rcap2l <= tl2;
    rcap2h <= th2;
  end
end
 
 
//
//
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    neg_trans <= 1'b0;
    t2ex_r <= 1'b0;
  end else if (t2ex) begin
    neg_trans <= 1'b0;
    t2ex_r <= 1'b1;
  end else if (t2ex_r) begin
    neg_trans <= 1'b1;
    t2ex_r <= 1'b0;
  end else begin
    neg_trans <= 1'b0;
    t2ex_r <= t2ex_r;
  end
end
 
//
//
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
    tc2_event <= 1'b0;
    t2_r <= 1'b0;
  end else if (t2) begin
    tc2_event <= 1'b0;
    t2_r <= 1'b1;
  end else if (!t2 & t2_r) begin
    tc2_event <= 1'b1;
    t2_r <= 1'b0;
  end else begin
    tc2_event <= 1'b0;
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores timer/counter2 control ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// timers and counters 2 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21			`//////////////////////////////////////////////////////////////////////`
22	2	dinesha	`//// ////`
23			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from http://www.opencores.org/lgpl.shtml ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47			`//`
48			`// CVS Revision History`
49			`//`
50			`// $Log: not supported by cvs2svn $`
51			`// Revision 1.2 2003/04/04 10:34:13 simont`
52			`// change timers to meet timing specifications (add divider with 12)`
53			`//`
54			`// Revision 1.1 2003/01/13 14:13:12 simont`
55			`// initial import`
56			`//`
57			`//`
58			`//`
59
60			`include "top_defines.v"
61
62
63
64	25	dinesha	`module oc8051_tc2 (clk, resetn,`
65	2	dinesha	`wr_addr,`
66			`data_in, bit_in,`
67			`wr, wr_bit,`
68			`t2, t2ex,`
69			`rclk, tclk,`
70			`brate2, tc2_int,`
71			`pres_ow,`
72			`//registers`
73			`t2con, tl2, th2, rcap2l, rcap2h);`
74
75			`input [7:0] wr_addr,`
76			`data_in;`
77			`input clk,`
78	25	dinesha	`resetn,`
79	2	dinesha	`wr,`
80			`wr_bit,`
81			`t2,`
82			`t2ex,`
83			`bit_in,`
84			`pres_ow; //prescalre owerflov`
85			`output [7:0] t2con,`
86			`tl2,`
87			`th2,`
88			`rcap2l,`
89			`rcap2h;`
90			`output tc2_int,`
91			`rclk,`
92			`tclk,`
93			`brate2;`
94
95
96			`reg brate2;`
97			`reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;`
98
99			`reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;`
100
101			`wire run;`
102
103			`//`
104			`// t2con`
105			`wire tf2, exf2, exen2, tr2, ct2, cprl2;`
106
107			`assign tc2_int = tf2 \| exf2;`
108			`assign tf2 = t2con[7];`
109			`assign exf2 = t2con[6];`
110			`assign rclk = t2con[5];`
111			`assign tclk = t2con[4];`
112			`assign exen2 = t2con[3];`
113			`assign tr2 = t2con[2];`
114			`assign ct2 = t2con[1];`
115			`assign cprl2 = t2con[0];`
116
117	25	dinesha	`always @(posedge clk or negedge resetn)`
118	2	dinesha	`begin`
119	25	dinesha	`if (resetn == 1'b0) begin`
120	36	dinesha	t2con <= `OC8051_RST_T2CON;
121	2	dinesha	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
122	36	dinesha	`t2con <= data_in;`
123	2	dinesha	end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
124	36	dinesha	`t2con[wr_addr[2:0]] <= bit_in;`
125	2	dinesha	`end else if (tf2_set) begin`
126	36	dinesha	`t2con[7] <= 1'b1;`
127	2	dinesha	`end else if (exen2 & neg_trans) begin`
128	36	dinesha	`t2con[6] <= 1'b1;`
129	2	dinesha	`end`
130			`end`
131
132
133			`//`
134			`//th2, tl2`
135			`assign run = tr2 & ((!ct2 & pres_ow) \| (ct2 & tc2_event));`
136
137	25	dinesha	`always @(posedge clk or negedge resetn)`
138	2	dinesha	`begin`
139	25	dinesha	`if (resetn == 1'b0) begin`
140	2	dinesha	`//`
141			`// reset`
142			`//`
143	36	dinesha	tl2 <= `OC8051_RST_TL2;
144			th2 <= `OC8051_RST_TH2;
145			`brate2 <= 1'b0;`
146			`tf2_set <= 1'b0;`
147	2	dinesha	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin
148			`//`
149			`// write to timer 2 high`
150			`//`
151	36	dinesha	`th2 <= data_in;`
152	2	dinesha	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
153			`//`
154			`// write to timer 2 low`
155			`//`
156	36	dinesha	`tl2 <= data_in;`
157	2	dinesha	`end else if (!(rclk \| tclk) & !cprl2 & exen2 & neg_trans) begin`
158			`//`
159			`// avto reload mode, exen2=1, 0-1 transition on t2ex pin`
160			`//`
161	36	dinesha	`th2 <= rcap2h;`
162			`tl2 <= rcap2l;`
163			`tf2_set <= 1'b0;`
164	2	dinesha	`end else if (run) begin`
165			`if (rclk \| tclk) begin`
166			`//`
167			`// boud rate generator mode`
168			`//`
169			`if (&{th2, tl2}) begin`
170	36	dinesha	`th2 <= rcap2h;`
171			`tl2 <= rcap2l;`
172			`brate2 <= 1'b1;`
173	2	dinesha	`end else begin`
174	36	dinesha	`{brate2, th2, tl2} <= {1'b0, th2, tl2} + 17'h1;`
175	2	dinesha	`end`
176	36	dinesha	`tf2_set <= 1'b0;`
177	2	dinesha	`end else if (cprl2) begin`
178			`//`
179			`// capture mode`
180			`//`
181	36	dinesha	`{tf2_set, th2, tl2} <= {1'b0, th2, tl2} + 17'h1;`
182	2	dinesha	`end else begin`
183			`//`
184			`// auto reload mode`
185			`//`
186			`if (&{th2, tl2}) begin`
187	36	dinesha	`th2 <= rcap2h;`
188			`tl2 <= rcap2l;`
189			`tf2_set <= 1'b1;`
190	2	dinesha	`end else begin`
191	36	dinesha	`{tf2_set, th2, tl2} <= {1'b0, th2, tl2} + 17'h1;`
192	2	dinesha	`end`
193			`end`
194	36	dinesha	`end else tf2_set <= 1'b0;`
195	2	dinesha	`end`
196
197
198			`//`
199			`// rcap2l, rcap2h`
200	25	dinesha	`always @(posedge clk or negedge resetn)`
201	2	dinesha	`begin`
202	25	dinesha	`if (resetn == 1'b0) begin`
203	36	dinesha	rcap2l <= `OC8051_RST_RCAP2L;
204			rcap2h <= `OC8051_RST_RCAP2H;
205	2	dinesha	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
206	36	dinesha	`rcap2h <= data_in;`
207	2	dinesha	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
208	36	dinesha	`rcap2l <= data_in;`
209	2	dinesha	`end else if (!(rclk \| tclk) & exen2 & cprl2 & neg_trans) begin`
210	36	dinesha	`rcap2l <= tl2;`
211			`rcap2h <= th2;`
212	2	dinesha	`end`
213			`end`
214
215
216			`//`
217			`//`
218	25	dinesha	`always @(posedge clk or negedge resetn)`
219	2	dinesha	`begin`
220	25	dinesha	`if (resetn == 1'b0) begin`
221	36	dinesha	`neg_trans <= 1'b0;`
222			`t2ex_r <= 1'b0;`
223	2	dinesha	`end else if (t2ex) begin`
224	36	dinesha	`neg_trans <= 1'b0;`
225			`t2ex_r <= 1'b1;`
226	2	dinesha	`end else if (t2ex_r) begin`
227	36	dinesha	`neg_trans <= 1'b1;`
228			`t2ex_r <= 1'b0;`
229	2	dinesha	`end else begin`
230	36	dinesha	`neg_trans <= 1'b0;`
231			`t2ex_r <= t2ex_r;`
232	2	dinesha	`end`
233			`end`
234
235			`//`
236			`//`
237	25	dinesha	`always @(posedge clk or negedge resetn)`
238	2	dinesha	`begin`
239	25	dinesha	`if (resetn == 1'b0) begin`
240	36	dinesha	`tc2_event <= 1'b0;`
241			`t2_r <= 1'b0;`
242	2	dinesha	`end else if (t2) begin`
243	36	dinesha	`tc2_event <= 1'b0;`
244			`t2_r <= 1'b1;`
245	2	dinesha	`end else if (!t2 & t2_r) begin`
246	36	dinesha	`tc2_event <= 1'b1;`
247			`t2_r <= 1'b0;`
248	2	dinesha	`end else begin`
249	36	dinesha	`tc2_event <= 1'b0;`
250	2	dinesha	`end`
251			`end`
252
253			`endmodule`

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_tc2.v] - Blame information for rev 36