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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores top level module                                 ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  8051 definitions.                                           ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 8th Dec 2016
////        1. External ROM Interface Removed
////   v0.1 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
////   v0.2 - Dinesh A, 6th Jan 2017
////        1. pc_next logic added
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.32  2003/06/20 13:36:37  simont
// ram modules added.
//
// Revision 1.31  2003/06/17 14:17:22  simont
// BIST signals added.
//
// Revision 1.30  2003/06/03 16:51:24  simont
// include "8051_defines" added.
//
// Revision 1.29  2003/05/07 12:36:03  simont
// chsnge comp.des to des1
//
// Revision 1.28  2003/05/06 09:41:35  simont
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
//
// Revision 1.27  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.26  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.25  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.24  2003/04/11 10:05:59  simont
// deifne OC8051_ROM added
//
// Revision 1.23  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.22  2003/04/09 16:24:04  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.21  2003/04/09 15:49:42  simont
// Register oc8051_sfr dato output, add signal wait_data.
//
// Revision 1.20  2003/04/03 19:13:28  simont
// Include instruction cache.
//
// Revision 1.19  2003/04/02 15:08:30  simont
// raname signals.
//
// Revision 1.18  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.17  2002/11/05 17:23:54  simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.16  2002/10/28 14:55:00  simont
// fix bug in interface to external data ram
//
// Revision 1.15  2002/10/23 16:53:39  simont
// fix bugs in instruction interface
//
// Revision 1.14  2002/10/17 18:50:00  simont
// cahnge interface to instruction rom
//
// Revision 1.13  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
`include "top_defines.v"
 
module oc8051_top (resetn, wb_clk_i,
 
//interface to data ram
                wbd_dat_i,
                wbd_dat_o,
                wbd_adr_o,
                wbd_we_o,
                wbd_ack_i,
                wbd_stb_o,
                wbd_cyc_o,
                wbd_err_i,
 
// interrupt interface
                int0_i,
                int1_i,
 
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
                p0_i,
                p0_o,
        `endif
 
        `ifdef OC8051_PORT1
                p1_i,
                p1_o,
        `endif
 
        `ifdef OC8051_PORT2
                p2_i,
                p2_o,
        `endif
 
        `ifdef OC8051_PORT3
                p3_i,
                p3_o,
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
                rxd_i, txd_o,
        `endif
 
// counter interface
        `ifdef OC8051_TC01
                t0_i, t1_i,
        `endif
 
        `ifdef OC8051_TC2
                t2_i, t2ex_i,
        `endif
 
// BIST
`ifdef OC8051_BIST
         scanb_rst,
         scanb_clk,
         scanb_si,
         scanb_so,
         scanb_en,
`endif
// external access (active low)
                ea_in
                );
 
 
 
input         resetn,         // reset input
              wb_clk_i,         // clock input
              int0_i,           // interrupt 0
              int1_i,           // interrupt 1
              ea_in,            // external access
              wbd_ack_i,        // data acknowalge
              wbd_err_i;        // data error
 
input [7:0]   wbd_dat_i;        // ram data input
 
output        wbd_we_o,         // data write enable
              wbd_stb_o,        // data strobe
              wbd_cyc_o;        // data cycle
 
output [7:0]  wbd_dat_o;        // data output
 
output [15:0] wbd_adr_o;        // data address
 
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
input  [7:0]  p0_i;             // port 0 input
output [7:0]  p0_o;             // port 0 output
`endif
 
`ifdef OC8051_PORT1
input  [7:0]  p1_i;             // port 1 input
output [7:0]  p1_o;             // port 1 output
`endif
 
`ifdef OC8051_PORT2
input  [7:0]  p2_i;             // port 2 input
output [7:0]  p2_o;             // port 2 output
`endif
 
`ifdef OC8051_PORT3
input  [7:0]  p3_i;             // port 3 input
output [7:0]  p3_o;             // port 3 output
`endif
 
`endif
 
 
 
 
 
 
`ifdef OC8051_UART
input         rxd_i;            // receive
output        txd_o;            // transnmit
`endif
 
`ifdef OC8051_TC01
input         t0_i,             // counter 0 input
              t1_i;             // counter 1 input
`endif
 
`ifdef OC8051_TC2
input         t2_i,             // counter 2 input
              t2ex_i;           //
`endif
 
`ifdef OC8051_BIST
input   scanb_rst;
input   scanb_clk;
input   scanb_si;
output  scanb_so;
input   scanb_en;
wire    scanb_soi;
`endif
 
wire [7:0]  dptr_hi,
            dptr_lo,
            ri,
            data_out,
            op1,
            op2,
            op3,
            acc,
            p0_out,
            p1_out,
            p2_out,
            p3_out,
            sp,
            sp_w;
 
wire [31:0] idat_onchip;
 
wire [15:0] pc,pc_next;
 
assign wbd_cyc_o = wbd_stb_o;
 
wire        src_sel3;
wire [1:0]  wr_sfr,
            src_sel2;
wire [2:0]  ram_rd_sel, // ram read
            ram_wr_sel, // ram write
            src_sel1;
 
wire [7:0]  ram_data,
            ram_out,    //data from ram
            sfr_out,
            wr_dat,
            wr_addr,    //ram write addres
            rd_addr;    //data ram read addres
wire        sfr_bit;
 
wire [1:0]  cy_sel,     //carry select; from decoder to cy_selct1
            bank_sel;
wire        rom_addr_sel,       //rom addres select; alu or pc
            rmw,
            ea_int;
 
wire        reti,
            intr,
            int_ack,
            istb;
wire [7:0]  int_src;
 
wire        mem_wait;
wire [2:0]  mem_act;
wire [3:0]  alu_op;     //alu operation (from decoder)
wire [1:0]  psw_set;    //write to psw or not; from decoder to psw (through register)
 
wire [7:0]  src1,       //alu sources 1
            src2,       //alu sources 2
            src3,       //alu sources 3
            des_acc,
            des1,       //alu destination 1
            des2;       //alu destinations 2
wire        desCy,      //carry out
            desAc,
            desOv,      //overflow
            alu_cy,
            wr,         //write to data ram
            wr_o;
 
wire        rd,         //read program rom
            pc_wr;
wire [2:0]  pc_wr_sel;  //program counter write select (from decoder to pc)
 
wire [7:0]  op1_n, //from memory_interface to decoder
            op2_n,
            op3_n;
 
wire [1:0]  comp_sel;   //select source1 and source2 to compare
wire        eq,         //result (from comp1 to decoder)
            srcAc,
            cy,
            rd_ind,
            wr_ind,
            comp_wait;
wire [2:0]  op1_cur;
 
wire        bit_addr,   //bit addresable instruction
            bit_data,   //bit data from ram to ram_select
            bit_out,    //bit data from ram_select to alu and cy_select
            bit_addr_o,
            wait_data;
 
//
// cpu to cache/wb_interface
wire [15:0] iadr_o;
 
 
//
// decoder
oc8051_decoder u_decoder(
          .clk                (wb_clk_i           ),
          .resetn                (resetn           ),
          .op_in              (op1_n              ),
          .op1_c              (op1_cur            ),
          .ram_rd_sel_o       (ram_rd_sel         ),
          .ram_wr_sel_o       (ram_wr_sel         ),
          .bit_addr           (bit_addr           ),
 
          .src_sel1           (src_sel1           ),
          .src_sel2           (src_sel2           ),
          .src_sel3           (src_sel3           ),
 
          .alu_op_o           (alu_op             ),
          .psw_set            (psw_set            ),
          .cy_sel             (cy_sel             ),
          .wr_o               (wr                 ),
          .pc_wr              (pc_wr              ),
          .pc_sel             (pc_wr_sel          ),
          .comp_sel           (comp_sel           ),
          .eq                 (eq                 ),
          .wr_sfr_o           (wr_sfr             ),
          .rd                 (rd                 ),
          .rmw                (rmw                ),
          .istb               (istb               ),
          .mem_act            (mem_act            ),
          .mem_wait           (mem_wait           ),
          .wait_data          (wait_data          )
     );
 
 
wire [7:0] sub_result;
//
//alu
oc8051_alu u_alu(
          .resetn                (resetn           ),
          .clk                (wb_clk_i           ),
          .op_code            (alu_op             ),
          .src1               (src1               ),
          .src2               (src2               ),
          .src3               (src3               ),
          .srcCy              (alu_cy             ),
          .srcAc              (srcAc              ),
          .des_acc            (des_acc            ),
          .sub_result         (sub_result         ),
          .des1               (des1               ),
          .des2               (des2               ),
          .desCy              (desCy              ),
          .desAc              (desAc              ),
          .desOv              (desOv              ),
          .bit_in(bit_out)
       );
 
//
//data ram
oc8051_ram_top u_ram_top(
          .clk                (wb_clk_i           ),
          .resetn                (resetn           ),
          .rd_addr            (rd_addr            ),
          .rd_data            (ram_data           ),
          .wr_addr            (wr_addr            ),
          .bit_addr           (bit_addr_o         ),
          .wr_data            (wr_dat             ),
          .wr                 (wr_o &&
                               (!wr_addr[7] || wr_ind)),
          .bit_data_in        (desCy              ),
          .bit_data_out       (bit_data           )
`ifdef OC8051_BIST
         ,
          .scanb_rst          (scanb_rst          ),
          .scanb_clk          (scanb_clk          ),
          .scanb_si           (scanb_soi          ),
          .scanb_so           (scanb_so           ),
          .scanb_en           (scanb_en           )
`endif
                               );
 
//
 
oc8051_alu_src_sel u_alu_src_sel(
          .clk                (wb_clk_i           ),
          .resetn                (resetn           ),
          .rd                 (rd                 ),
 
          .sel1               (src_sel1           ),
          .sel2               (src_sel2           ),
          .sel3               (src_sel3           ),
 
          .acc                (acc                ),
          .ram                (ram_out            ),
          .pc                 (pc_next            ),
          .dptr               ({dptr_hi, dptr_lo} ),
          .op1                (op1_n              ),
          .op2                (op2_n              ),
          .op3                (op3_n              ),
 
          .src1               (src1               ),
          .src2               (src2               ),
          .src3               (src3               )
      );
 
 
//
//
oc8051_comp u_comp(
          .sel                (comp_sel           ),
          .eq                 (eq                 ),
          .b_in               (bit_out            ),
          .cy                 (cy                 ),
          .acc                (acc                ),
          .des                (sub_result         )
    );
 
 
//
//program rom
`ifdef OC8051_ROM
  oc8051_rom u_rom(
          .resetn                (resetn           ),
          .clk                (wb_clk_i           ),
          .ea_int             (ea_int             ),
          .addr               (iadr_o             ),
          .data_o             (idat_onchip        )
     );
`else
  assign ea_int = 1'b0;
  assign idat_onchip = 32'h0;
 
  `ifdef OC8051_SIMULATION
 
    initial
    begin
      $display("\t * ");
      $display("\t * Internal rom disabled!!!");
      $display("\t * ");
    end
 
  `endif
 
`endif
 
//
//
oc8051_cy_select u_cy_select(
          .cy_sel             (cy_sel             ),
          .cy_in              (cy                 ),
          .data_in            (bit_out            ),
          .data_out           (alu_cy             )
    );
//
//
oc8051_indi_addr u_indi_addr (
          .clk                (wb_clk_i           ),
          .resetn                (resetn           ),
          .wr_addr            (wr_addr            ),
          .data_in            (wr_dat             ),
          .wr                 (wr_o               ),
          .wr_bit             (bit_addr_o         ),
          .ri_out             (ri                 ),
          .sel                (op1_cur[0]         ),
          .bank               (bank_sel           )
 );
 
 
 
//
//
oc8051_memory_interface u_memory_interface(
          .clk                (wb_clk_i           ),
          .resetn                (resetn           ),
// internal ram
          .wr_i               (wr                 ),
          .wr_o               (wr_o               ),
          .wr_bit_i           (bit_addr           ),
          .wr_bit_o           (bit_addr_o         ),
          .wr_dat             (wr_dat             ),
          .des_acc            (des_acc            ),
          .des1               (des1               ),
          .des2               (des2               ),
          .rd_addr            (rd_addr            ),
          .wr_addr            (wr_addr            ),
          .wr_ind             (wr_ind             ),
          .bit_in             (bit_data           ),
          .in_ram             (ram_data           ),
          .sfr                (sfr_out            ),
          .sfr_bit            (sfr_bit            ),
          .bit_out            (bit_out            ),
          .iram_out           (ram_out            ),
 
// external instrauction rom
          .iadr_o             (iadr_o             ),
 
// internal instruction rom
          .idat_onchip        (idat_onchip        ),
 
// data memory
          .dadr_o             (wbd_adr_o          ),
          .ddat_o             (wbd_dat_o          ),
          .dwe_o              (wbd_we_o           ),
          .dstb_o             (wbd_stb_o          ),
          .ddat_i             (wbd_dat_i          ),
          .dack_i             (wbd_ack_i          ),
 
// from decoder
          .rd_sel             (ram_rd_sel         ),
          .wr_sel             (ram_wr_sel         ),
          .rn                 ({bank_sel, op1_cur}),
          .rd_ind             (rd_ind             ),
          .rd                 (rd                 ),
          .mem_act            (mem_act            ),
          .mem_wait           (mem_wait           ),
 
// external access
          .ea                 (ea_in              ),
          .ea_int             (ea_int             ),
 
// instructions outputs to cpu
          .op1_out            (op1_n              ),
          .op2_out            (op2_n              ),
          .op3_out            (op3_n              ),
 
// interrupt interface
          .intr               (intr               ),
                       .int_v(int_src),
          .int_ack            (int_ack            ),
          .istb               (istb               ),
          .reti               (reti               ),
 
//pc
          .pc_wr_sel          (pc_wr_sel          ),
          .pc_wr              (pc_wr & comp_wait  ),
          .pc                 (pc                 ),
          .pc_next            (pc_next            ),
 
// sfr's
          .sp_w               (sp_w               ),
          .dptr               ({dptr_hi, dptr_lo} ),
          .ri                 (ri                 ),
          .acc                (acc                ),
          .sp                 (sp                 )
       );
 
 
//
//
 
oc8051_sfr u_sfr(
          .resetn                (resetn           ),
          .clk                (wb_clk_i           ),
          .adr0               (rd_addr[7:0]       ),
          .adr1               (wr_addr[7:0]       ),
          .dat0               (sfr_out            ),
          .dat1               (wr_dat             ),
          .dat2               (des2               ),
          .des_acc            (des_acc            ),
          .we                 (wr_o && !wr_ind    ),
          .bit_in             (desCy              ),
          .bit_out            (sfr_bit            ),
          .wr_bit             (bit_addr_o         ),
          .ram_rd_sel         (ram_rd_sel         ),
          .ram_wr_sel         (ram_wr_sel         ),
          .wr_sfr             (wr_sfr             ),
          .comp_sel           (comp_sel           ),
          .comp_wait          (comp_wait          ),
// acc
          .acc                (acc                ),
// sp
          .sp                 (sp                 ),
          .sp_w               (sp_w               ),
// psw
          .bank_sel           (bank_sel           ),
          .desAc              (desAc              ),
          .desOv              (desOv              ),
          .psw_set            (psw_set            ),
          .srcAc              (srcAc              ),
          .cy                 (cy                 ),
// ports
          .rmw                (rmw                ),
 
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
          .p0_out             (p0_o               ),
          .p0_in              (p0_i               ),
        `endif
 
        `ifdef OC8051_PORT1
          .p1_out             (p1_o               ),
          .p1_in              (p1_i               ),
        `endif
 
        `ifdef OC8051_PORT2
          .p2_out             (p2_o               ),
          .p2_in              (p2_i               ),
        `endif
 
        `ifdef OC8051_PORT3
          .p3_out             (p3_o               ),
          .p3_in              (p3_i               ),
        `endif
  `endif
 
// uart
        `ifdef OC8051_UART
          .rxd                (rxd_i              ),
          .txd                (txd_o              ),
        `endif
 
// int
          .int_ack            (int_ack            ),
          .intr               (intr               ),
          .int0               (int0_i             ),
          .int1               (int1_i             ),
          .reti               (reti               ),
          .int_src            (int_src            ),
 
// t/c 0,1
        `ifdef OC8051_TC01
          .t0                 (t0_i               ),
          .t1                 (t1_i               ),
        `endif
 
// t/c 2
        `ifdef OC8051_TC2
          .t2                 (t2_i               ),
          .t2ex               (t2ex_i             ),
        `endif
 
// dptr
          .dptr_hi            (dptr_hi            ),
          .dptr_lo            (dptr_lo            ),
          .wait_data          (wait_data          )
       );
 
 
  `ifdef OC8051_BIST
       assign scanb_soi=scanb_si;
  `endif
 
 
 
  `ifdef OC8051_SIMULATION
 
    initial
    begin
      #1
      $display("\t * ");
      $display("\t * External rom interface: Pipelined interface");
      $display("\t * ");
    end
 
  `endif
 
 
 
 
 
// synopsys translate_off
// Debug Purpose only
// Stack Pointer Push & Pop analysis
reg [7:0]   StackMem[$];
reg  [7:0]  stack_pop;
reg  [7:0]  pushpop_cnt;
 
// Assumption, Both Write and Read access will not be
// possbile in single clock cycle
always @(posedge wb_clk_i or negedge resetn)
begin
   if(resetn == 1'b0) begin
      pushpop_cnt = 0;
   end
   else begin
      if(ram_wr_sel==`OC8051_RWS_SP) begin
            StackMem.push_back(wr_dat);
            pushpop_cnt = pushpop_cnt + 1;
      end
      if(ram_rd_sel==`OC8051_RRS_SP) begin
            stack_pop = StackMem.pop_back();
            pushpop_cnt = pushpop_cnt - 1;
            #2  // Add 1ns Delay to take care of Ram Dealy
            if(stack_pop != ram_data) begin
              $display("ERROR: Invalid Stack Pointer Pop Detected, Exp: %x,Rxd:%x",stack_pop,ram_data);
              $stop;
            end
      end
   end
end
 
// synopsys translate_on
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17	11	dinesha	`//////////////////////////////////////////////////////////////////////`
18	18	dinesha	`//// v0.0 - Dinesh A, 8th Dec 2016`
19			`//// 1. External ROM Interface Removed`
20	25	dinesha	`//// v0.1 - Dinesh A, 5th Jan 2017`
21			`//// 1. Active edge of reset changed from High to Low`
22	26	dinesha	`//// v0.2 - Dinesh A, 6th Jan 2017`
23			`//// 1. pc_next logic added`
24	2	dinesha	`//// ////`
25			`//////////////////////////////////////////////////////////////////////`
26			`//// ////`
27			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
28			`//// ////`
29			`//// This source file may be used and distributed without ////`
30			`//// restriction provided that this copyright statement is not ////`
31			`//// removed from the file and that any derivative work contains ////`
32			`//// the original copyright notice and the associated disclaimer. ////`
33			`//// ////`
34			`//// This source file is free software; you can redistribute it ////`
35			`//// and/or modify it under the terms of the GNU Lesser General ////`
36			`//// Public License as published by the Free Software Foundation; ////`
37			`//// either version 2.1 of the License, or (at your option) any ////`
38			`//// later version. ////`
39			`//// ////`
40			`//// This source is distributed in the hope that it will be ////`
41			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
42			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
43			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
44			`//// details. ////`
45			`//// ////`
46			`//// You should have received a copy of the GNU Lesser General ////`
47			`//// Public License along with this source; if not, download it ////`
48			`//// from http://www.opencores.org/lgpl.shtml ////`
49			`//// ////`
50			`//////////////////////////////////////////////////////////////////////`
51			`//`
52			`// CVS Revision History`
53			`//`
54			`// $Log: not supported by cvs2svn $`
55			`// Revision 1.32 2003/06/20 13:36:37 simont`
56			`// ram modules added.`
57			`//`
58			`// Revision 1.31 2003/06/17 14:17:22 simont`
59			`// BIST signals added.`
60			`//`
61			`// Revision 1.30 2003/06/03 16:51:24 simont`
62			`// include "8051_defines" added.`
63			`//`
64			`// Revision 1.29 2003/05/07 12:36:03 simont`
65			`// chsnge comp.des to des1`
66			`//`
67			`// Revision 1.28 2003/05/06 09:41:35 simont`
68			`// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.`
69			`//`
70			`// Revision 1.27 2003/05/05 15:46:37 simont`
71			`// add aditional alu destination to solve critical path.`
72			`//`
73			`// Revision 1.26 2003/04/29 11:24:31 simont`
74			`// fix bug in case execution of two data dependent instructions.`
75			`//`
76			`// Revision 1.25 2003/04/25 17:15:51 simont`
77			`// change branch instruction execution (reduse needed clock periods).`
78			`//`
79			`// Revision 1.24 2003/04/11 10:05:59 simont`
80			`// deifne OC8051_ROM added`
81			`//`
82			`// Revision 1.23 2003/04/10 12:43:19 simont`
83			`// defines for pherypherals added`
84			`//`
85			`// Revision 1.22 2003/04/09 16:24:04 simont`
86			`// change wr_sft to 2 bit wire.`
87			`//`
88			`// Revision 1.21 2003/04/09 15:49:42 simont`
89			`// Register oc8051_sfr dato output, add signal wait_data.`
90			`//`
91			`// Revision 1.20 2003/04/03 19:13:28 simont`
92			`// Include instruction cache.`
93			`//`
94			`// Revision 1.19 2003/04/02 15:08:30 simont`
95			`// raname signals.`
96			`//`
97			`// Revision 1.18 2003/01/13 14:14:41 simont`
98			`// replace some modules`
99			`//`
100			`// Revision 1.17 2002/11/05 17:23:54 simont`
101			`// add module oc8051_sfr, 256 bytes internal ram`
102			`//`
103			`// Revision 1.16 2002/10/28 14:55:00 simont`
104			`// fix bug in interface to external data ram`
105			`//`
106			`// Revision 1.15 2002/10/23 16:53:39 simont`
107			`// fix bugs in instruction interface`
108			`//`
109			`// Revision 1.14 2002/10/17 18:50:00 simont`
110			`// cahnge interface to instruction rom`
111			`//`
112			`// Revision 1.13 2002/09/30 17:33:59 simont`
113			`// prepared header`
114			`//`
115			`//`
116
117
118			`include "top_defines.v"
119
120	25	dinesha	`module oc8051_top (resetn, wb_clk_i,`
121	2	dinesha
122			`//interface to data ram`
123			`wbd_dat_i,`
124			`wbd_dat_o,`
125			`wbd_adr_o,`
126			`wbd_we_o,`
127			`wbd_ack_i,`
128			`wbd_stb_o,`
129			`wbd_cyc_o,`
130			`wbd_err_i,`
131
132			`// interrupt interface`
133			`int0_i,`
134			`int1_i,`
135
136
137			`// port interface`
138			`ifdef OC8051_PORTS
139			`ifdef OC8051_PORT0
140			`p0_i,`
141			`p0_o,`
142			`endif
143
144			`ifdef OC8051_PORT1
145			`p1_i,`
146			`p1_o,`
147			`endif
148
149			`ifdef OC8051_PORT2
150			`p2_i,`
151			`p2_o,`
152			`endif
153
154			`ifdef OC8051_PORT3
155			`p3_i,`
156			`p3_o,`
157			`endif
158			`endif
159
160			`// serial interface`
161			`ifdef OC8051_UART
162			`rxd_i, txd_o,`
163			`endif
164
165			`// counter interface`
166			`ifdef OC8051_TC01
167			`t0_i, t1_i,`
168			`endif
169
170			`ifdef OC8051_TC2
171			`t2_i, t2ex_i,`
172			`endif
173
174			`// BIST`
175			`ifdef OC8051_BIST
176			`scanb_rst,`
177			`scanb_clk,`
178			`scanb_si,`
179			`scanb_so,`
180			`scanb_en,`
181			`endif
182			`// external access (active low)`
183			`ea_in`
184			`);`
185
186
187
188	25	dinesha	`input resetn, // reset input`
189	2	dinesha	`wb_clk_i, // clock input`
190			`int0_i, // interrupt 0`
191			`int1_i, // interrupt 1`
192			`ea_in, // external access`
193			`wbd_ack_i, // data acknowalge`
194	11	dinesha	`wbd_err_i; // data error`
195	2	dinesha
196			`input [7:0] wbd_dat_i; // ram data input`
197
198			`output wbd_we_o, // data write enable`
199			`wbd_stb_o, // data strobe`
200	11	dinesha	`wbd_cyc_o; // data cycle`
201	2	dinesha
202			`output [7:0] wbd_dat_o; // data output`
203
204	11	dinesha	`output [15:0] wbd_adr_o; // data address`
205	2	dinesha
206			`ifdef OC8051_PORTS
207
208			`ifdef OC8051_PORT0
209			`input [7:0] p0_i; // port 0 input`
210			`output [7:0] p0_o; // port 0 output`
211			`endif
212
213			`ifdef OC8051_PORT1
214			`input [7:0] p1_i; // port 1 input`
215			`output [7:0] p1_o; // port 1 output`
216			`endif
217
218			`ifdef OC8051_PORT2
219			`input [7:0] p2_i; // port 2 input`
220			`output [7:0] p2_o; // port 2 output`
221			`endif
222
223			`ifdef OC8051_PORT3
224			`input [7:0] p3_i; // port 3 input`
225			`output [7:0] p3_o; // port 3 output`
226			`endif
227
228			`endif
229
230
231
232
233
234
235			`ifdef OC8051_UART
236			`input rxd_i; // receive`
237			`output txd_o; // transnmit`
238			`endif
239
240			`ifdef OC8051_TC01
241			`input t0_i, // counter 0 input`
242			`t1_i; // counter 1 input`
243			`endif
244
245			`ifdef OC8051_TC2
246			`input t2_i, // counter 2 input`
247			`t2ex_i; //`
248			`endif
249
250			`ifdef OC8051_BIST
251			`input scanb_rst;`
252			`input scanb_clk;`
253			`input scanb_si;`
254			`output scanb_so;`
255			`input scanb_en;`
256			`wire scanb_soi;`
257			`endif
258
259			`wire [7:0] dptr_hi,`
260			`dptr_lo,`
261			`ri,`
262			`data_out,`
263			`op1,`
264			`op2,`
265			`op3,`
266			`acc,`
267			`p0_out,`
268			`p1_out,`
269			`p2_out,`
270			`p3_out,`
271			`sp,`
272			`sp_w;`
273
274			`wire [31:0] idat_onchip;`
275
276	26	dinesha	`wire [15:0] pc,pc_next;`
277	2	dinesha
278			`assign wbd_cyc_o = wbd_stb_o;`
279
280			`wire src_sel3;`
281			`wire [1:0] wr_sfr,`
282			`src_sel2;`
283			`wire [2:0] ram_rd_sel, // ram read`
284			`ram_wr_sel, // ram write`
285			`src_sel1;`
286
287			`wire [7:0] ram_data,`
288			`ram_out, //data from ram`
289			`sfr_out,`
290			`wr_dat,`
291			`wr_addr, //ram write addres`
292			`rd_addr; //data ram read addres`
293			`wire sfr_bit;`
294
295			`wire [1:0] cy_sel, //carry select; from decoder to cy_selct1`
296			`bank_sel;`
297			`wire rom_addr_sel, //rom addres select; alu or pc`
298			`rmw,`
299			`ea_int;`
300
301			`wire reti,`
302			`intr,`
303			`int_ack,`
304			`istb;`
305			`wire [7:0] int_src;`
306
307			`wire mem_wait;`
308			`wire [2:0] mem_act;`
309			`wire [3:0] alu_op; //alu operation (from decoder)`
310			`wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)`
311
312			`wire [7:0] src1, //alu sources 1`
313			`src2, //alu sources 2`
314			`src3, //alu sources 3`
315			`des_acc,`
316			`des1, //alu destination 1`
317			`des2; //alu destinations 2`
318			`wire desCy, //carry out`
319			`desAc,`
320			`desOv, //overflow`
321			`alu_cy,`
322			`wr, //write to data ram`
323			`wr_o;`
324
325			`wire rd, //read program rom`
326			`pc_wr;`
327			`wire [2:0] pc_wr_sel; //program counter write select (from decoder to pc)`
328
329			`wire [7:0] op1_n, //from memory_interface to decoder`
330			`op2_n,`
331			`op3_n;`
332
333			`wire [1:0] comp_sel; //select source1 and source2 to compare`
334			`wire eq, //result (from comp1 to decoder)`
335			`srcAc,`
336			`cy,`
337			`rd_ind,`
338			`wr_ind,`
339			`comp_wait;`
340			`wire [2:0] op1_cur;`
341
342			`wire bit_addr, //bit addresable instruction`
343			`bit_data, //bit data from ram to ram_select`
344			`bit_out, //bit data from ram_select to alu and cy_select`
345			`bit_addr_o,`
346			`wait_data;`
347
348			`//`
349			`// cpu to cache/wb_interface`
350			`wire [15:0] iadr_o;`
351
352
353			`//`
354			`// decoder`
355	20	dinesha	`oc8051_decoder u_decoder(`
356	2	dinesha	`.clk (wb_clk_i ),`
357	25	dinesha	`.resetn (resetn ),`
358	2	dinesha	`.op_in (op1_n ),`
359			`.op1_c (op1_cur ),`
360			`.ram_rd_sel_o (ram_rd_sel ),`
361			`.ram_wr_sel_o (ram_wr_sel ),`
362			`.bit_addr (bit_addr ),`
363
364			`.src_sel1 (src_sel1 ),`
365			`.src_sel2 (src_sel2 ),`
366			`.src_sel3 (src_sel3 ),`
367
368			`.alu_op_o (alu_op ),`
369			`.psw_set (psw_set ),`
370			`.cy_sel (cy_sel ),`
371			`.wr_o (wr ),`
372			`.pc_wr (pc_wr ),`
373			`.pc_sel (pc_wr_sel ),`
374			`.comp_sel (comp_sel ),`
375			`.eq (eq ),`
376			`.wr_sfr_o (wr_sfr ),`
377			`.rd (rd ),`
378			`.rmw (rmw ),`
379			`.istb (istb ),`
380			`.mem_act (mem_act ),`
381			`.mem_wait (mem_wait ),`
382			`.wait_data (wait_data )`
383			`);`
384
385
386			`wire [7:0] sub_result;`
387			`//`
388			`//alu`
389	20	dinesha	`oc8051_alu u_alu(`
390	25	dinesha	`.resetn (resetn ),`
391	2	dinesha	`.clk (wb_clk_i ),`
392			`.op_code (alu_op ),`
393			`.src1 (src1 ),`
394			`.src2 (src2 ),`
395			`.src3 (src3 ),`
396			`.srcCy (alu_cy ),`
397			`.srcAc (srcAc ),`
398			`.des_acc (des_acc ),`
399			`.sub_result (sub_result ),`
400			`.des1 (des1 ),`
401			`.des2 (des2 ),`
402			`.desCy (desCy ),`
403			`.desAc (desAc ),`
404			`.desOv (desOv ),`
405			`.bit_in(bit_out)`
406			`);`
407
408			`//`
409			`//data ram`
410	20	dinesha	`oc8051_ram_top u_ram_top(`
411	2	dinesha	`.clk (wb_clk_i ),`
412	25	dinesha	`.resetn (resetn ),`
413	2	dinesha	`.rd_addr (rd_addr ),`
414			`.rd_data (ram_data ),`
415			`.wr_addr (wr_addr ),`
416			`.bit_addr (bit_addr_o ),`
417			`.wr_data (wr_dat ),`
418			`.wr (wr_o &&`
419			`(!wr_addr[7] \|\| wr_ind)),`
420			`.bit_data_in (desCy ),`
421			`.bit_data_out (bit_data )`
422			`ifdef OC8051_BIST
423			`,`
424			`.scanb_rst (scanb_rst ),`
425			`.scanb_clk (scanb_clk ),`
426			`.scanb_si (scanb_soi ),`
427			`.scanb_so (scanb_so ),`
428			`.scanb_en (scanb_en )`
429			`endif
430			`);`
431
432			`//`
433
434	20	dinesha	`oc8051_alu_src_sel u_alu_src_sel(`
435	2	dinesha	`.clk (wb_clk_i ),`
436	25	dinesha	`.resetn (resetn ),`
437	2	dinesha	`.rd (rd ),`
438
439			`.sel1 (src_sel1 ),`
440			`.sel2 (src_sel2 ),`
441			`.sel3 (src_sel3 ),`
442
443			`.acc (acc ),`
444			`.ram (ram_out ),`
445	26	dinesha	`.pc (pc_next ),`
446	2	dinesha	`.dptr ({dptr_hi, dptr_lo} ),`
447			`.op1 (op1_n ),`
448			`.op2 (op2_n ),`
449			`.op3 (op3_n ),`
450
451			`.src1 (src1 ),`
452			`.src2 (src2 ),`
453			`.src3 (src3 )`
454			`);`
455
456
457			`//`
458			`//`
459	20	dinesha	`oc8051_comp u_comp(`
460	2	dinesha	`.sel (comp_sel ),`
461			`.eq (eq ),`
462			`.b_in (bit_out ),`
463			`.cy (cy ),`
464			`.acc (acc ),`
465			`.des (sub_result )`
466			`);`
467
468
469			`//`
470			`//program rom`
471			`ifdef OC8051_ROM
472	20	dinesha	`oc8051_rom u_rom(`
473	25	dinesha	`.resetn (resetn ),`
474	2	dinesha	`.clk (wb_clk_i ),`
475			`.ea_int (ea_int ),`
476			`.addr (iadr_o ),`
477			`.data_o (idat_onchip )`
478			`);`
479			`else
480			`assign ea_int = 1'b0;`
481			`assign idat_onchip = 32'h0;`
482
483			`ifdef OC8051_SIMULATION
484
485			`initial`
486			`begin`
487			`$display("\t * ");`
488			`$display("\t * Internal rom disabled!!!");`
489			`$display("\t * ");`
490			`end`
491
492			`endif
493
494			`endif
495
496			`//`
497			`//`
498	20	dinesha	`oc8051_cy_select u_cy_select(`
499	2	dinesha	`.cy_sel (cy_sel ),`
500			`.cy_in (cy ),`

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