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[/] [oms8051mini/] [trunk/] [rtl/] [clkgen/] [clkgen.v] - Blame information for rev 25

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS 8051 cores clockgen Module                              ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : Nov 26, 2016                                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
module clkgen (
               reset_n      ,
               fastsim_mode ,
               mastermode   ,
               xtal_clk     ,
               clkout       ,
               gen_resetn   ,
               risc_resetn  ,
               app_clk      ,
               uart_ref_clk
              );
 
 
 
input           reset_n      ; // Async reset signal
input         fastsim_mode   ; // fast sim mode = 1
input         mastermode     ; // 1 : Risc master mode
input           xtal_clk     ; // Xtal clock-25Mhx 
output        clkout         ; // clock output, 250Mhz
output        gen_resetn     ; // internally generated reset
output        risc_resetn    ; // internally generated reset
output        app_clk        ; // application clock
output        uart_ref_clk   ; // uart 16x Ref clock
 
 
wire          hard_reset_st  ;
wire          configure_st   ;
wire          wait_pll_st    ;
wire          run_st         ;
wire          slave_run_st   ;
reg           pll_done       ;
reg [11:0]         pll_count  ;
reg [2:0]          clkgen_ps  ;
reg           gen_resetn     ; // internally generated reset
reg           risc_resetn    ; // internally generated reset
 
 
assign        clkout = app_clk;
wire          pllout;
/***********************************************
 Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz
*********************************************************/
/*******************
altera_stargate_pll u_pll (
        . areset     (!reset_n ),
        . inclk0     (xtal_clk),
        . c0         (pllout),
        . locked     ()
       );
*************************/
 
assign pllout = xtal_clk;
 
//---------------------------------------------
//
// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)
 
//--------------------------------------------
always @(posedge xtal_clk or negedge reset_n)
   begin // {
      if (!reset_n)
      begin // {
         pll_count <= 12'h9C4;
      end   // }                                                                 
      else if (configure_st)
      begin // {
         pll_count <= (fastsim_mode) ? 12'h040  :  12'h9C4;
      end // }
      else if (wait_pll_st)
      begin // {
         pll_count <= (pll_done) ? pll_count : (pll_count - 1'b1);
     end // }
   end // }
 
 
/************************************************
    PLL Timer Counter
************************************************/
 
always @(posedge xtal_clk or negedge reset_n)
begin
   if (!reset_n)
      pll_done <= 0;
   else if (pll_count == 16'h0)
      pll_done <= 1;
   else if (configure_st)
      pll_done <= 0;
end
 
 
/************************************************
  internally generated reset
************************************************/
always @(posedge xtal_clk or negedge reset_n )
begin
   if (!reset_n) begin
      gen_resetn  <=  0;
      risc_resetn <=  0;
   end else if(run_st ) begin
      gen_resetn  <=  1;
      risc_resetn <=  1;
   end else if(slave_run_st ) begin
      gen_resetn  <=  1;
      risc_resetn <=  0; // Keet Risc in Reset
   end else begin
      gen_resetn  <=  0;
      risc_resetn <=  0;
   end
end
 
 
/****************************************
    Reset State Machine
****************************************/
/*****************************************
   Define Clock Gen stat machine state
*****************************************/
`define HARD_RESET      3'b000
`define CONFIGURE       3'b001
`define WAIT_PLL        3'b010
`define RUN             3'b011
`define SLAVE_RUN       3'b100
 
assign hard_reset_st     = (clkgen_ps == `HARD_RESET);
assign configure_st      = (clkgen_ps == `CONFIGURE);
assign wait_pll_st       = (clkgen_ps == `WAIT_PLL);
assign run_st            = (clkgen_ps == `RUN);
assign slave_run_st      = (clkgen_ps == `SLAVE_RUN);
 
always @(posedge xtal_clk or negedge reset_n)
begin
   if (!reset_n) begin
      clkgen_ps <= `HARD_RESET;
   end
   else begin
      case (clkgen_ps)
         `HARD_RESET:
            clkgen_ps <= `CONFIGURE;
 
          `CONFIGURE:
             clkgen_ps <= `WAIT_PLL;
 
         `WAIT_PLL:
           if (pll_done) begin
              if ( mastermode )
                             clkgen_ps <= `RUN;
                    else
                             clkgen_ps <= `SLAVE_RUN;
          end
      endcase
   end
end
 
 
//----------------------------------
// Generate Application clock 125Mhz
//----------------------------------
 
clk_ctl #(1) u_appclk (
   // Outputs
       .clk_o         (app_clk),
   // Inputs
       .mclk          (pllout),
       .reset_n       (gen_resetn),
       .clk_div_ratio (2'b00)
   );
 
 
//----------------------------------
// Generate Uart Ref Clock clock 50Mhz
// 200Mhz/(2+0) = 50Mhz
// 250Mhz/(2+3) = 50Mhz
//----------------------------------
 
clk_ctl #(2) u_uart_clk (
   // Outputs
       .clk_o         (uart_ref_clk),
 
   // Inputs
       .mclk          (pllout      ),
       .reset_n       (gen_resetn  ),
       .clk_div_ratio (3'b000      )
   );
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OMS 8051 cores clockgen Module ////`
4			`//// ////`
5			`//// This file is part of the OMS 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OMS 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : Nov 26, 2016 ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
21			`//// 1. Active edge of reset changed from High to Low`
22			`//////////////////////////////////////////////////////////////////////`
23	2	dinesha	`//// ////`
24			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`//////////////////////////////////////////////////////////////////////`
48
49
50			`module clkgen (`
51			`reset_n ,`
52			`fastsim_mode ,`
53			`mastermode ,`
54			`xtal_clk ,`
55			`clkout ,`
56			`gen_resetn ,`
57	25	dinesha	`risc_resetn ,`
58	2	dinesha	`app_clk ,`
59			`uart_ref_clk`
60			`);`
61
62
63
64	25	dinesha	`input reset_n ; // Async reset signal`
65	2	dinesha	`input fastsim_mode ; // fast sim mode = 1`
66			`input mastermode ; // 1 : Risc master mode`
67	25	dinesha	`input xtal_clk ; // Xtal clock-25Mhx`
68	2	dinesha	`output clkout ; // clock output, 250Mhz`
69			`output gen_resetn ; // internally generated reset`
70	25	dinesha	`output risc_resetn ; // internally generated reset`
71	2	dinesha	`output app_clk ; // application clock`
72			`output uart_ref_clk ; // uart 16x Ref clock`
73
74
75			`wire hard_reset_st ;`
76			`wire configure_st ;`
77			`wire wait_pll_st ;`
78			`wire run_st ;`
79			`wire slave_run_st ;`
80			`reg pll_done ;`
81	25	dinesha	`reg [11:0] pll_count ;`
82			`reg [2:0] clkgen_ps ;`
83	2	dinesha	`reg gen_resetn ; // internally generated reset`
84	25	dinesha	`reg risc_resetn ; // internally generated reset`
85	2	dinesha
86
87			`assign clkout = app_clk;`
88			`wire pllout;`
89			`/***********************************************`
90			`Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz`
91			`*********************************************************/`
92			`/*******************`
93			`altera_stargate_pll u_pll (`
94			`. areset (!reset_n ),`
95			`. inclk0 (xtal_clk),`
96			`. c0 (pllout),`
97			`. locked ()`
98			`);`
99			`*************************/`
100
101			`assign pllout = xtal_clk;`
102
103			`//---------------------------------------------`
104			`//`
105			`// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)`
106
107			`//--------------------------------------------`
108			`always @(posedge xtal_clk or negedge reset_n)`
109			`begin // {`
110			`if (!reset_n)`
111			`begin // {`
112			`pll_count <= 12'h9C4;`
113			`end // }`
114			`else if (configure_st)`
115			`begin // {`
116			`pll_count <= (fastsim_mode) ? 12'h040 : 12'h9C4;`
117			`end // }`
118			`else if (wait_pll_st)`
119			`begin // {`
120			`pll_count <= (pll_done) ? pll_count : (pll_count - 1'b1);`
121			`end // }`
122			`end // }`
123
124
125			`/************************************************`
126			`PLL Timer Counter`
127			`************************************************/`
128
129			`always @(posedge xtal_clk or negedge reset_n)`
130			`begin`
131			`if (!reset_n)`
132			`pll_done <= 0;`
133			`else if (pll_count == 16'h0)`
134			`pll_done <= 1;`
135			`else if (configure_st)`
136			`pll_done <= 0;`
137			`end`
138
139
140			`/************************************************`
141			`internally generated reset`
142			`************************************************/`
143			`always @(posedge xtal_clk or negedge reset_n )`
144			`begin`
145			`if (!reset_n) begin`
146			`gen_resetn <= 0;`
147	25	dinesha	`risc_resetn <= 0;`
148	2	dinesha	`end else if(run_st ) begin`
149			`gen_resetn <= 1;`
150	25	dinesha	`risc_resetn <= 1;`
151	2	dinesha	`end else if(slave_run_st ) begin`
152			`gen_resetn <= 1;`
153	25	dinesha	`risc_resetn <= 0; // Keet Risc in Reset`
154	2	dinesha	`end else begin`
155			`gen_resetn <= 0;`
156	25	dinesha	`risc_resetn <= 0;`
157	2	dinesha	`end`
158			`end`
159
160
161			`/****************************************`
162			`Reset State Machine`
163			`****************************************/`
164			`/*****************************************`
165			`Define Clock Gen stat machine state`
166			`*****************************************/`
167			`define HARD_RESET 3'b000
168			`define CONFIGURE 3'b001
169			`define WAIT_PLL 3'b010
170			`define RUN 3'b011
171			`define SLAVE_RUN 3'b100
172
173			assign hard_reset_st = (clkgen_ps == `HARD_RESET);
174			assign configure_st = (clkgen_ps == `CONFIGURE);
175			assign wait_pll_st = (clkgen_ps == `WAIT_PLL);
176			assign run_st = (clkgen_ps == `RUN);
177			assign slave_run_st = (clkgen_ps == `SLAVE_RUN);
178
179			`always @(posedge xtal_clk or negedge reset_n)`
180			`begin`
181			`if (!reset_n) begin`
182			clkgen_ps <= `HARD_RESET;
183			`end`
184			`else begin`
185			`case (clkgen_ps)`
186			`HARD_RESET:
187			clkgen_ps <= `CONFIGURE;
188
189			`CONFIGURE:
190			clkgen_ps <= `WAIT_PLL;
191
192			`WAIT_PLL:
193			`if (pll_done) begin`
194			`if ( mastermode )`
195			clkgen_ps <= `RUN;
196			`else`
197			clkgen_ps <= `SLAVE_RUN;
198			`end`
199			`endcase`
200			`end`
201			`end`
202
203
204			`//----------------------------------`
205			`// Generate Application clock 125Mhz`
206			`//----------------------------------`
207
208			`clk_ctl #(1) u_appclk (`
209			`// Outputs`
210			`.clk_o (app_clk),`
211			`// Inputs`
212			`.mclk (pllout),`
213			`.reset_n (gen_resetn),`
214			`.clk_div_ratio (2'b00)`
215			`);`
216
217
218			`//----------------------------------`
219			`// Generate Uart Ref Clock clock 50Mhz`
220			`// 200Mhz/(2+0) = 50Mhz`
221			`// 250Mhz/(2+3) = 50Mhz`
222			`//----------------------------------`
223
224			`clk_ctl #(2) u_uart_clk (`
225			`// Outputs`
226			`.clk_o (uart_ref_clk),`
227
228			`// Inputs`
229			`.mclk (pllout ),`
230			`.reset_n (gen_resetn ),`
231			`.clk_div_ratio (3'b000 )`
232			`);`
233
234
235
236			`endmodule`

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[/] [oms8051mini/] [trunk/] [rtl/] [clkgen/] [clkgen.v] - Blame information for rev 25