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[/] [oms8051mini/] [trunk/] [rtl/] [i2cm/] [i2cm_bit_ctrl.v] - Blame information for rev 28

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS8051 I2C Master bit-controller Module                    ////
////  WISHBONE rev.B2 compliant I2C Master bit-controller         ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      -Richard Herveille ,  richard@asics.ws, www.asics.ws    ////
////      -Dinesh Annayya, dinesha@opencores.org                  ////
////                                                              ////
////  Revision : Jan 6, 2017                                      //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//     v0.0 - Dinesh A, 6th Jan 2017
//          1. Initail version picked from
//              http://www.opencores.org/projects/i2c/
//
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
/////////////////////////////////////
// Bit controller section
/////////////////////////////////////
//
// Translate simple commands into SCL/SDA transitions
// Each command has 5 states, A/B/C/D/idle
//
// start:       SCL     ~~~~~~~~~~\____
//      SDA     ~~~~~~~~\______
//               x | A | B | C | D | i
//
// repstart     SCL     ____/~~~~\___
//      SDA     __/~~~\______
//               x | A | B | C | D | i
//
// stop SCL     ____/~~~~~~~~
//      SDA     ==\____/~~~~~
//               x | A | B | C | D | i
//
//- write       SCL     ____/~~~~\____
//      SDA     ==X=========X=
//               x | A | B | C | D | i
//
//- read        SCL     ____/~~~~\____
//      SDA     XXXX=====XXXX
//               x | A | B | C | D | i
//
 
// Timing:     Normal mode      Fast mode
///////////////////////////////////////////////////////////////////////
// Fscl        100KHz           400KHz
// Th_scl      4.0us            0.6us   High period of SCL
// Tl_scl      4.7us            1.3us   Low period of SCL
// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
//
 
 
`include "i2cm_defines.v"
 
module i2cm_bit_ctrl (
    input             clk,      // system clock
    input             sresetn,  // synchronous active low reset
    input             aresetn,  // asynchronous active low reset
    input             ena,      // core enable signal
 
    input      [15:0] clk_cnt,  // clock prescale value
 
    input      [ 3:0] cmd,      // command (from byte controller)
    output reg        cmd_ack,  // command complete acknowledge
    output reg        busy,     // i2c bus busy
    output reg        al,       // i2c bus arbitration lost
 
    input             din,
    output reg        dout,
 
    input             scl_i,    // i2c clock line input
    output            scl_o,    // i2c clock line output
    output reg        scl_oen,  // i2c clock line output enable (active low)
    input             sda_i,    // i2c data line input
    output            sda_o,    // i2c data line output
    output reg        sda_oen   // i2c data line output enable (active low)
);
 
 
    //
    // variable declarations
    //
 
    reg [ 1:0] cSCL, cSDA;      // capture SCL and SDA
    reg [ 2:0] fSCL, fSDA;      // SCL and SDA filter inputs
    reg        sSCL, sSDA;      // filtered and synchronized SCL and SDA inputs
    reg        dSCL, dSDA;      // delayed versions of sSCL and sSDA
    reg        dscl_oen;        // delayed scl_oen
    reg        sda_chk;         // check SDA output (Multi-master arbitration)
    reg        clk_en;          // clock generation signals
    reg        slave_wait;      // slave inserts wait states
    reg [15:0] cnt;             // clock divider counter (synthesis)
    reg [13:0] filter_cnt;      // clock divider for filter
 
 
    // state machine variable
    reg [17:0] c_state; // synopsys enum_state
 
    //
    // module body
    //
 
    // whenever the slave is not ready it can delay the cycle by pulling SCL low
    // delay scl_oen
    always @(posedge clk)
      dscl_oen <= #1 scl_oen;
 
    // slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
    // slave_wait remains asserted until the slave releases SCL
    always @(posedge clk or negedge aresetn)
      if (!aresetn) slave_wait <= 1'b0;
      else         slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
 
    // master drives SCL high, but another master pulls it low
    // master start counting down its low cycle now (clock synchronization)
    wire scl_sync   = dSCL & ~sSCL & scl_oen;
 
 
    // generate clk enable signal
    always @(posedge clk or negedge aresetn)
      if (~aresetn)
      begin
          cnt    <= #1 16'h0;
          clk_en <= #1 1'b1;
      end
      else if (!sresetn || ~|cnt || !ena || scl_sync)
      begin
          cnt    <= #1 clk_cnt;
          clk_en <= #1 1'b1;
      end
      else if (slave_wait)
      begin
          cnt    <= #1 cnt;
          clk_en <= #1 1'b0;
      end
      else
      begin
          cnt    <= #1 cnt - 16'h1;
          clk_en <= #1 1'b0;
      end
 
 
    // generate bus status controller
 
    // capture SDA and SCL
    // reduce metastability risk
    always @(posedge clk or negedge aresetn)
      if (!aresetn)
      begin
          cSCL <= #1 2'b00;
          cSDA <= #1 2'b00;
      end
      else if (!sresetn)
      begin
          cSCL <= #1 2'b00;
          cSDA <= #1 2'b00;
      end
      else
      begin
          cSCL <= {cSCL[0],scl_i};
          cSDA <= {cSDA[0],sda_i};
      end
 
 
    // filter SCL and SDA signals; (attempt to) remove glitches
    always @(posedge clk or negedge aresetn)
      if      (!aresetn     ) filter_cnt <= 14'h0;
      else if (!sresetn || !ena ) filter_cnt <= 14'h0;
      else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency
      else                   filter_cnt <= filter_cnt -1;
 
 
    always @(posedge clk or negedge aresetn)
      if (!aresetn)
      begin
          fSCL <= 3'b111;
          fSDA <= 3'b111;
      end
      else if (!sresetn)
      begin
          fSCL <= 3'b111;
          fSDA <= 3'b111;
      end
      else if (~|filter_cnt)
      begin
          fSCL <= {fSCL[1:0],cSCL[1]};
          fSDA <= {fSDA[1:0],cSDA[1]};
      end
 
 
    // generate filtered SCL and SDA signals
    always @(posedge clk or negedge aresetn)
      if (~aresetn)
      begin
          sSCL <= #1 1'b1;
          sSDA <= #1 1'b1;
 
          dSCL <= #1 1'b1;
          dSDA <= #1 1'b1;
      end
      else if (!sresetn)
      begin
          sSCL <= #1 1'b1;
          sSDA <= #1 1'b1;
 
          dSCL <= #1 1'b1;
          dSDA <= #1 1'b1;
      end
      else
      begin
          sSCL <= #1 &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
          sSDA <= #1 &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
 
          dSCL <= #1 sSCL;
          dSDA <= #1 sSDA;
      end
 
    // detect start condition => detect falling edge on SDA while SCL is high
    // detect stop condition => detect rising edge on SDA while SCL is high
    reg sta_condition;
    reg sto_condition;
    always @(posedge clk or negedge aresetn)
      if (~aresetn)
      begin
          sta_condition <= #1 1'b0;
          sto_condition <= #1 1'b0;
      end
      else if (!sresetn)
      begin
          sta_condition <= #1 1'b0;
          sto_condition <= #1 1'b0;
      end
      else
      begin
          sta_condition <= #1 ~sSDA &  dSDA & sSCL;
          sto_condition <= #1  sSDA & ~dSDA & sSCL;
      end
 
 
    // generate i2c bus busy signal
    always @(posedge clk or negedge aresetn)
      if      (!aresetn) busy <= #1 1'b0;
      else if (!sresetn    ) busy <= #1 1'b0;
      else              busy <= #1 (sta_condition | busy) & ~sto_condition;
 
 
    // generate arbitration lost signal
    // aribitration lost when:
    // 1) master drives SDA high, but the i2c bus is low
    // 2) stop detected while not requested
    reg cmd_stop;
    always @(posedge clk or negedge aresetn)
      if (~aresetn)
          cmd_stop <= #1 1'b0;
      else if (!sresetn)
          cmd_stop <= #1 1'b0;
      else if (clk_en)
          cmd_stop <= #1 cmd == `I2C_CMD_STOP;
 
    always @(posedge clk or negedge aresetn)
      if (~aresetn)
          al <= #1 1'b0;
      else if (!sresetn)
          al <= #1 1'b0;
      else
          al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
 
 
    // generate dout signal (store SDA on rising edge of SCL)
    always @(posedge clk)
      if (sSCL & ~dSCL) dout <= #1 sSDA;
 
 
    // generate statemachine
 
    // nxt_state decoder
    parameter [17:0] idle    = 18'b0_0000_0000_0000_0000;
    parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
    parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
    parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
    parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
    parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
    parameter [17:0] stop_a  = 18'b0_0000_0000_0010_0000;
    parameter [17:0] stop_b  = 18'b0_0000_0000_0100_0000;
    parameter [17:0] stop_c  = 18'b0_0000_0000_1000_0000;
    parameter [17:0] stop_d  = 18'b0_0000_0001_0000_0000;
    parameter [17:0] rd_a    = 18'b0_0000_0010_0000_0000;
    parameter [17:0] rd_b    = 18'b0_0000_0100_0000_0000;
    parameter [17:0] rd_c    = 18'b0_0000_1000_0000_0000;
    parameter [17:0] rd_d    = 18'b0_0001_0000_0000_0000;
    parameter [17:0] wr_a    = 18'b0_0010_0000_0000_0000;
    parameter [17:0] wr_b    = 18'b0_0100_0000_0000_0000;
    parameter [17:0] wr_c    = 18'b0_1000_0000_0000_0000;
    parameter [17:0] wr_d    = 18'b1_0000_0000_0000_0000;
 
    always @(posedge clk or negedge aresetn)
      if (!aresetn)
      begin
          c_state <= #1 idle;
          cmd_ack <= #1 1'b0;
          scl_oen <= #1 1'b1;
          sda_oen <= #1 1'b1;
          sda_chk <= #1 1'b0;
      end
      else if (!sresetn | al)
      begin
          c_state <= #1 idle;
          cmd_ack <= #1 1'b0;
          scl_oen <= #1 1'b1;
          sda_oen <= #1 1'b1;
          sda_chk <= #1 1'b0;
      end
      else
      begin
          cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
 
          if (clk_en)
              case (c_state) // synopsys full_case parallel_case
                    // idle state
                    idle:
                    begin
                        case (cmd) // synopsys full_case parallel_case
                             `I2C_CMD_START: c_state <= #1 start_a;
                             `I2C_CMD_STOP:  c_state <= #1 stop_a;
                             `I2C_CMD_WRITE: c_state <= #1 wr_a;
                             `I2C_CMD_READ:  c_state <= #1 rd_a;
                             default:        c_state <= #1 idle;
                        endcase
 
                        scl_oen <= #1 scl_oen; // keep SCL in same state
                        sda_oen <= #1 sda_oen; // keep SDA in same state
                        sda_chk <= #1 1'b0;    // don't check SDA output
                    end
 
                    // start
                    start_a:
                    begin
                        c_state <= #1 start_b;
                        scl_oen <= #1 scl_oen; // keep SCL in same state
                        sda_oen <= #1 1'b1;    // set SDA high
                        sda_chk <= #1 1'b0;    // don't check SDA output
                    end
 
                    start_b:
                    begin
                        c_state <= #1 start_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 1'b1; // keep SDA high
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    start_c:
                    begin
                        c_state <= #1 start_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b0; // set SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    start_d:
                    begin
                        c_state <= #1 start_e;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    start_e:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b0; // set SCL low
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    // stop
                    stop_a:
                    begin
                        c_state <= #1 stop_b;
                        scl_oen <= #1 1'b0; // keep SCL low
                        sda_oen <= #1 1'b0; // set SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    stop_b:
                    begin
                        c_state <= #1 stop_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    stop_c:
                    begin
                        c_state <= #1 stop_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b0; // keep SDA low
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    stop_d:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b1; // set SDA high
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    // read
                    rd_a:
                    begin
                        c_state <= #1 rd_b;
                        scl_oen <= #1 1'b0; // keep SCL low
                        sda_oen <= #1 1'b1; // tri-state SDA
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    rd_b:
                    begin
                        c_state <= #1 rd_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 1'b1; // keep SDA tri-stated
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    rd_c:
                    begin
                        c_state <= #1 rd_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 1'b1; // keep SDA tri-stated
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    rd_d:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b0; // set SCL low
                        sda_oen <= #1 1'b1; // keep SDA tri-stated
                        sda_chk <= #1 1'b0; // don't check SDA output
                    end
 
                    // write
                    wr_a:
                    begin
                        c_state <= #1 wr_b;
                        scl_oen <= #1 1'b0; // keep SCL low
                        sda_oen <= #1 din;  // set SDA
                        sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
                    end
 
                    wr_b:
                    begin
                        c_state <= #1 wr_c;
                        scl_oen <= #1 1'b1; // set SCL high
                        sda_oen <= #1 din;  // keep SDA
                        sda_chk <= #1 1'b0; // don't check SDA output yet
                                            // allow some time for SDA and SCL to settle
                    end
 
                    wr_c:
                    begin
                        c_state <= #1 wr_d;
                        scl_oen <= #1 1'b1; // keep SCL high
                        sda_oen <= #1 din;
                        sda_chk <= #1 1'b1; // check SDA output
                    end
 
                    wr_d:
                    begin
                        c_state <= #1 idle;
                        cmd_ack <= #1 1'b1;
                        scl_oen <= #1 1'b0; // set SCL low
                        sda_oen <= #1 din;
                        sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
                    end
 
              endcase
      end
 
 
    // assign scl and sda output (always gnd)
    assign scl_o = 1'b0;
    assign sda_o = 1'b0;
 
endmodule

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Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [rtl/] [i2cm/] [i2cm_bit_ctrl.v] - Blame information for rev 28

Line No.	Rev	Author	Line
1	28	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OMS8051 I2C Master bit-controller Module ////`
4			`//// WISHBONE rev.B2 compliant I2C Master bit-controller ////`
5			`//// ////`
6			`//// This file is part of the OMS 8051 cores project ////`
7			`//// http://www.opencores.org/cores/oms8051mini/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// OMS 8051 definitions. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// -Richard Herveille , richard@asics.ws, www.asics.ws ////`
17			`//// -Dinesh Annayya, dinesha@opencores.org ////`
18			`//// ////`
19			`//// Revision : Jan 6, 2017 ////`
20			`//// ////`
21			`//////////////////////////////////////////////////////////////////////`
22			`// v0.0 - Dinesh A, 6th Jan 2017`
23			`// 1. Initail version picked from`
24			`// http://www.opencores.org/projects/i2c/`
25			`//`
26			`//////////////////////////////////////////////////////////////////////`
27			`//// ////`
28			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
29			`//// ////`
30			`//// This source file may be used and distributed without ////`
31			`//// restriction provided that this copyright statement is not ////`
32			`//// removed from the file and that any derivative work contains ////`
33			`//// the original copyright notice and the associated disclaimer. ////`
34			`//// ////`
35			`//// This source file is free software; you can redistribute it ////`
36			`//// and/or modify it under the terms of the GNU Lesser General ////`
37			`//// Public License as published by the Free Software Foundation; ////`
38			`//// either version 2.1 of the License, or (at your option) any ////`
39			`//// later version. ////`
40			`//// ////`
41			`//// This source is distributed in the hope that it will be ////`
42			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
43			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
44			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
45			`//// details. ////`
46			`//// ////`
47			`//// You should have received a copy of the GNU Lesser General ////`
48			`//// Public License along with this source; if not, download it ////`
49			`//// from http://www.opencores.org/lgpl.shtml ////`
50			`//// ////`
51			`//////////////////////////////////////////////////////////////////////`
52			`/////////////////////////////////////`
53			`// Bit controller section`
54			`/////////////////////////////////////`
55			`//`
56			`// Translate simple commands into SCL/SDA transitions`
57			`// Each command has 5 states, A/B/C/D/idle`
58			`//`
59			`// start: SCL ~~~~~~~~~~\____`
60			`// SDA ~~~~~~~~\______`
61			`// x \| A \| B \| C \| D \| i`
62			`//`
63			`// repstart SCL ____/~~~~\___`
64			`// SDA __/~~~\______`
65			`// x \| A \| B \| C \| D \| i`
66			`//`
67			`// stop SCL ____/~~~~~~~~`
68			`// SDA ==\____/~~~~~`
69			`// x \| A \| B \| C \| D \| i`
70			`//`
71			`//- write SCL ____/~~~~\____`
72			`// SDA ==X=========X=`
73			`// x \| A \| B \| C \| D \| i`
74			`//`
75			`//- read SCL ____/~~~~\____`
76			`// SDA XXXX=====XXXX`
77			`// x \| A \| B \| C \| D \| i`
78			`//`
79
80			`// Timing: Normal mode Fast mode`
81			`///////////////////////////////////////////////////////////////////////`
82			`// Fscl 100KHz 400KHz`
83			`// Th_scl 4.0us 0.6us High period of SCL`
84			`// Tl_scl 4.7us 1.3us Low period of SCL`
85			`// Tsu:sta 4.7us 0.6us setup time for a repeated start condition`
86			`// Tsu:sto 4.0us 0.6us setup time for a stop conditon`
87			`// Tbuf 4.7us 1.3us Bus free time between a stop and start condition`
88			`//`
89
90
91			`include "i2cm_defines.v"
92
93			`module i2cm_bit_ctrl (`
94			`input clk, // system clock`
95			`input sresetn, // synchronous active low reset`
96			`input aresetn, // asynchronous active low reset`
97			`input ena, // core enable signal`
98
99			`input [15:0] clk_cnt, // clock prescale value`
100
101			`input [ 3:0] cmd, // command (from byte controller)`
102			`output reg cmd_ack, // command complete acknowledge`
103			`output reg busy, // i2c bus busy`
104			`output reg al, // i2c bus arbitration lost`
105
106			`input din,`
107			`output reg dout,`
108
109			`input scl_i, // i2c clock line input`
110			`output scl_o, // i2c clock line output`
111			`output reg scl_oen, // i2c clock line output enable (active low)`
112			`input sda_i, // i2c data line input`
113			`output sda_o, // i2c data line output`
114			`output reg sda_oen // i2c data line output enable (active low)`
115			`);`
116
117
118			`//`
119			`// variable declarations`
120			`//`
121
122			`reg [ 1:0] cSCL, cSDA; // capture SCL and SDA`
123			`reg [ 2:0] fSCL, fSDA; // SCL and SDA filter inputs`
124			`reg sSCL, sSDA; // filtered and synchronized SCL and SDA inputs`
125			`reg dSCL, dSDA; // delayed versions of sSCL and sSDA`
126			`reg dscl_oen; // delayed scl_oen`
127			`reg sda_chk; // check SDA output (Multi-master arbitration)`
128			`reg clk_en; // clock generation signals`
129			`reg slave_wait; // slave inserts wait states`
130			`reg [15:0] cnt; // clock divider counter (synthesis)`
131			`reg [13:0] filter_cnt; // clock divider for filter`
132
133
134			`// state machine variable`
135			`reg [17:0] c_state; // synopsys enum_state`
136
137			`//`
138			`// module body`
139			`//`
140
141			`// whenever the slave is not ready it can delay the cycle by pulling SCL low`
142			`// delay scl_oen`
143			`always @(posedge clk)`
144			`dscl_oen <= #1 scl_oen;`
145
146			`// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low`
147			`// slave_wait remains asserted until the slave releases SCL`
148			`always @(posedge clk or negedge aresetn)`
149			`if (!aresetn) slave_wait <= 1'b0;`
150			`else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) \| (slave_wait & ~sSCL);`
151
152			`// master drives SCL high, but another master pulls it low`
153			`// master start counting down its low cycle now (clock synchronization)`
154			`wire scl_sync = dSCL & ~sSCL & scl_oen;`
155
156
157			`// generate clk enable signal`
158			`always @(posedge clk or negedge aresetn)`
159			`if (~aresetn)`
160			`begin`
161			`cnt <= #1 16'h0;`
162			`clk_en <= #1 1'b1;`
163			`end`
164			`else if (!sresetn \|\| ~\|cnt \|\| !ena \|\| scl_sync)`
165			`begin`
166			`cnt <= #1 clk_cnt;`
167			`clk_en <= #1 1'b1;`
168			`end`
169			`else if (slave_wait)`
170			`begin`
171			`cnt <= #1 cnt;`
172			`clk_en <= #1 1'b0;`
173			`end`
174			`else`
175			`begin`
176			`cnt <= #1 cnt - 16'h1;`
177			`clk_en <= #1 1'b0;`
178			`end`
179
180
181			`// generate bus status controller`
182
183			`// capture SDA and SCL`
184			`// reduce metastability risk`
185			`always @(posedge clk or negedge aresetn)`
186			`if (!aresetn)`
187			`begin`
188			`cSCL <= #1 2'b00;`
189			`cSDA <= #1 2'b00;`
190			`end`
191			`else if (!sresetn)`
192			`begin`
193			`cSCL <= #1 2'b00;`
194			`cSDA <= #1 2'b00;`
195			`end`
196			`else`
197			`begin`
198			`cSCL <= {cSCL[0],scl_i};`
199			`cSDA <= {cSDA[0],sda_i};`
200			`end`
201
202
203			`// filter SCL and SDA signals; (attempt to) remove glitches`
204			`always @(posedge clk or negedge aresetn)`
205			`if (!aresetn ) filter_cnt <= 14'h0;`
206			`else if (!sresetn \|\| !ena ) filter_cnt <= 14'h0;`
207			`else if (~\|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency`
208			`else filter_cnt <= filter_cnt -1;`
209
210
211			`always @(posedge clk or negedge aresetn)`
212			`if (!aresetn)`
213			`begin`
214			`fSCL <= 3'b111;`
215			`fSDA <= 3'b111;`
216			`end`
217			`else if (!sresetn)`
218			`begin`
219			`fSCL <= 3'b111;`
220			`fSDA <= 3'b111;`
221			`end`
222			`else if (~\|filter_cnt)`
223			`begin`
224			`fSCL <= {fSCL[1:0],cSCL[1]};`
225			`fSDA <= {fSDA[1:0],cSDA[1]};`
226			`end`
227
228
229			`// generate filtered SCL and SDA signals`
230			`always @(posedge clk or negedge aresetn)`
231			`if (~aresetn)`
232			`begin`
233			`sSCL <= #1 1'b1;`
234			`sSDA <= #1 1'b1;`
235
236			`dSCL <= #1 1'b1;`
237			`dSDA <= #1 1'b1;`
238			`end`
239			`else if (!sresetn)`
240			`begin`
241			`sSCL <= #1 1'b1;`
242			`sSDA <= #1 1'b1;`
243
244			`dSCL <= #1 1'b1;`
245			`dSDA <= #1 1'b1;`
246			`end`
247			`else`
248			`begin`
249			`sSCL <= #1 &fSCL[2:1] \| &fSCL[1:0] \| (fSCL[2] & fSCL[0]);`
250			`sSDA <= #1 &fSDA[2:1] \| &fSDA[1:0] \| (fSDA[2] & fSDA[0]);`
251
252			`dSCL <= #1 sSCL;`
253			`dSDA <= #1 sSDA;`
254			`end`
255
256			`// detect start condition => detect falling edge on SDA while SCL is high`
257			`// detect stop condition => detect rising edge on SDA while SCL is high`
258			`reg sta_condition;`
259			`reg sto_condition;`
260			`always @(posedge clk or negedge aresetn)`
261			`if (~aresetn)`
262			`begin`
263			`sta_condition <= #1 1'b0;`
264			`sto_condition <= #1 1'b0;`
265			`end`
266			`else if (!sresetn)`
267			`begin`
268			`sta_condition <= #1 1'b0;`
269			`sto_condition <= #1 1'b0;`
270			`end`
271			`else`
272			`begin`
273			`sta_condition <= #1 ~sSDA & dSDA & sSCL;`
274			`sto_condition <= #1 sSDA & ~dSDA & sSCL;`
275			`end`
276
277
278			`// generate i2c bus busy signal`
279			`always @(posedge clk or negedge aresetn)`
280			`if (!aresetn) busy <= #1 1'b0;`
281			`else if (!sresetn ) busy <= #1 1'b0;`
282			`else busy <= #1 (sta_condition \| busy) & ~sto_condition;`
283
284
285			`// generate arbitration lost signal`
286			`// aribitration lost when:`
287			`// 1) master drives SDA high, but the i2c bus is low`
288			`// 2) stop detected while not requested`
289			`reg cmd_stop;`
290			`always @(posedge clk or negedge aresetn)`
291			`if (~aresetn)`
292			`cmd_stop <= #1 1'b0;`
293			`else if (!sresetn)`
294			`cmd_stop <= #1 1'b0;`
295			`else if (clk_en)`
296			cmd_stop <= #1 cmd == `I2C_CMD_STOP;
297
298			`always @(posedge clk or negedge aresetn)`
299			`if (~aresetn)`
300			`al <= #1 1'b0;`
301			`else if (!sresetn)`
302			`al <= #1 1'b0;`
303			`else`
304			`al <= #1 (sda_chk & ~sSDA & sda_oen) \| (\|c_state & sto_condition & ~cmd_stop);`
305
306
307			`// generate dout signal (store SDA on rising edge of SCL)`
308			`always @(posedge clk)`
309			`if (sSCL & ~dSCL) dout <= #1 sSDA;`
310
311
312			`// generate statemachine`
313
314			`// nxt_state decoder`
315			`parameter [17:0] idle = 18'b0_0000_0000_0000_0000;`
316			`parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;`
317			`parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;`
318			`parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;`
319			`parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;`
320			`parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;`
321			`parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;`
322			`parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;`
323			`parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;`
324			`parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;`
325			`parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;`
326			`parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;`
327			`parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;`
328			`parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;`
329			`parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;`
330			`parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;`
331			`parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;`
332			`parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;`
333
334			`always @(posedge clk or negedge aresetn)`
335			`if (!aresetn)`
336			`begin`
337			`c_state <= #1 idle;`
338			`cmd_ack <= #1 1'b0;`
339			`scl_oen <= #1 1'b1;`
340			`sda_oen <= #1 1'b1;`
341			`sda_chk <= #1 1'b0;`
342			`end`
343			`else if (!sresetn \| al)`
344			`begin`
345			`c_state <= #1 idle;`
346			`cmd_ack <= #1 1'b0;`
347			`scl_oen <= #1 1'b1;`
348			`sda_oen <= #1 1'b1;`
349			`sda_chk <= #1 1'b0;`
350			`end`
351			`else`
352			`begin`
353			`cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle`
354
355			`if (clk_en)`
356			`case (c_state) // synopsys full_case parallel_case`
357			`// idle state`
358			`idle:`
359			`begin`
360			`case (cmd) // synopsys full_case parallel_case`
361			`I2C_CMD_START: c_state <= #1 start_a;
362			`I2C_CMD_STOP: c_state <= #1 stop_a;
363			`I2C_CMD_WRITE: c_state <= #1 wr_a;
364			`I2C_CMD_READ: c_state <= #1 rd_a;
365			`default: c_state <= #1 idle;`
366			`endcase`
367
368			`scl_oen <= #1 scl_oen; // keep SCL in same state`
369			`sda_oen <= #1 sda_oen; // keep SDA in same state`
370			`sda_chk <= #1 1'b0; // don't check SDA output`
371			`end`
372
373			`// start`
374			`start_a:`
375			`begin`
376			`c_state <= #1 start_b;`
377			`scl_oen <= #1 scl_oen; // keep SCL in same state`
378			`sda_oen <= #1 1'b1; // set SDA high`
379			`sda_chk <= #1 1'b0; // don't check SDA output`
380			`end`
381
382			`start_b:`
383			`begin`
384			`c_state <= #1 start_c;`
385			`scl_oen <= #1 1'b1; // set SCL high`
386			`sda_oen <= #1 1'b1; // keep SDA high`
387			`sda_chk <= #1 1'b0; // don't check SDA output`
388			`end`
389
390			`start_c:`
391			`begin`
392			`c_state <= #1 start_d;`
393			`scl_oen <= #1 1'b1; // keep SCL high`
394			`sda_oen <= #1 1'b0; // set SDA low`
395			`sda_chk <= #1 1'b0; // don't check SDA output`
396			`end`
397
398			`start_d:`
399			`begin`
400			`c_state <= #1 start_e;`
401			`scl_oen <= #1 1'b1; // keep SCL high`
402			`sda_oen <= #1 1'b0; // keep SDA low`
403			`sda_chk <= #1 1'b0; // don't check SDA output`
404			`end`
405
406			`start_e:`
407			`begin`
408			`c_state <= #1 idle;`
409			`cmd_ack <= #1 1'b1;`
410			`scl_oen <= #1 1'b0; // set SCL low`
411			`sda_oen <= #1 1'b0; // keep SDA low`
412			`sda_chk <= #1 1'b0; // don't check SDA output`
413			`end`
414
415			`// stop`
416			`stop_a:`
417			`begin`
418			`c_state <= #1 stop_b;`
419			`scl_oen <= #1 1'b0; // keep SCL low`
420			`sda_oen <= #1 1'b0; // set SDA low`
421			`sda_chk <= #1 1'b0; // don't check SDA output`
422			`end`
423
424			`stop_b:`
425			`begin`
426			`c_state <= #1 stop_c;`
427			`scl_oen <= #1 1'b1; // set SCL high`
428			`sda_oen <= #1 1'b0; // keep SDA low`
429			`sda_chk <= #1 1'b0; // don't check SDA output`
430			`end`
431
432			`stop_c:`
433			`begin`
434			`c_state <= #1 stop_d;`
435			`scl_oen <= #1 1'b1; // keep SCL high`
436			`sda_oen <= #1 1'b0; // keep SDA low`
437			`sda_chk <= #1 1'b0; // don't check SDA output`
438			`end`
439
440			`stop_d:`
441			`begin`
442			`c_state <= #1 idle;`
443			`cmd_ack <= #1 1'b1;`
444			`scl_oen <= #1 1'b1; // keep SCL high`
445			`sda_oen <= #1 1'b1; // set SDA high`
446			`sda_chk <= #1 1'b0; // don't check SDA output`
447			`end`
448
449			`// read`
450			`rd_a:`
451			`begin`
452			`c_state <= #1 rd_b;`
453			`scl_oen <= #1 1'b0; // keep SCL low`
454			`sda_oen <= #1 1'b1; // tri-state SDA`
455			`sda_chk <= #1 1'b0; // don't check SDA output`
456			`end`
457
458			`rd_b:`
459			`begin`
460			`c_state <= #1 rd_c;`
461			`scl_oen <= #1 1'b1; // set SCL high`
462			`sda_oen <= #1 1'b1; // keep SDA tri-stated`
463			`sda_chk <= #1 1'b0; // don't check SDA output`
464			`end`
465
466			`rd_c:`
467			`begin`
468			`c_state <= #1 rd_d;`
469			`scl_oen <= #1 1'b1; // keep SCL high`
470			`sda_oen <= #1 1'b1; // keep SDA tri-stated`
471			`sda_chk <= #1 1'b0; // don't check SDA output`
472			`end`
473
474			`rd_d:`
475			`begin`
476			`c_state <= #1 idle;`
477			`cmd_ack <= #1 1'b1;`
478			`scl_oen <= #1 1'b0; // set SCL low`
479			`sda_oen <= #1 1'b1; // keep SDA tri-stated`
480			`sda_chk <= #1 1'b0; // don't check SDA output`
481			`end`
482
483			`// write`
484			`wr_a:`
485			`begin`
486			`c_state <= #1 wr_b;`
487			`scl_oen <= #1 1'b0; // keep SCL low`
488			`sda_oen <= #1 din; // set SDA`
489			`sda_chk <= #1 1'b0; // don't check SDA output (SCL low)`
490			`end`
491
492			`wr_b:`
493			`begin`
494			`c_state <= #1 wr_c;`
495			`scl_oen <= #1 1'b1; // set SCL high`
496			`sda_oen <= #1 din; // keep SDA`
497			`sda_chk <= #1 1'b0; // don't check SDA output yet`
498			`// allow some time for SDA and SCL to settle`
499			`end`
500
501			`wr_c:`
502			`begin`
503			`c_state <= #1 wr_d;`
504			`scl_oen <= #1 1'b1; // keep SCL high`
505			`sda_oen <= #1 din;`
506			`sda_chk <= #1 1'b1; // check SDA output`
507			`end`
508
509			`wr_d:`
510			`begin`
511			`c_state <= #1 idle;`
512			`cmd_ack <= #1 1'b1;`
513			`scl_oen <= #1 1'b0; // set SCL low`
514			`sda_oen <= #1 din;`
515			`sda_chk <= #1 1'b0; // don't check SDA output (SCL low)`
516			`end`
517
518			`endcase`
519			`end`
520
521
522			`// assign scl and sda output (always gnd)`
523			`assign scl_o = 1'b0;`
524			`assign sda_o = 1'b0;`
525
526			`endmodule`