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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS8051 I2C Master byte-controller Module                  ////
////  WISHBONE rev.B2 compliant I2C Master byte-controller       ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      -Richard Herveille ,  richard@asics.ws, www.asics.ws    ////
////      -Dinesh Annayya, dinesha@opencores.org                  ////
////                                                              ////
////  Revision : Jan 6, 2017                                      //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//     v0.0 - Dinesh A, 6th Jan 2017
//          1. Initail version picked from
//              http://www.opencores.org/projects/i2c/
//          2. renaming of reset signal to aresetn and sresetn
//
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "i2cm_defines.v"
 
module i2cm_byte_ctrl (
        //
        // inputs & outputs
        //
        input        clk,     // master clock
        input        sresetn, // synchronous active high reset
        input        aresetn, // asynchronous active low reset
        input        ena,     // core enable signal
 
        input [15:0] clk_cnt, // 4x SCL
 
        // control inputs
        input        start,
        input        stop,
        input        read,
        input        write,
        input        ack_in,
        input [7:0]  din,
 
        // status outputs
        output reg   cmd_ack,
        output reg   ack_out,
        output       i2c_busy,
        output       i2c_al,
        output [7:0] dout,
 
        // I2C signals
        input        scl_i,
        output       scl_o,
        output       scl_oen,
        input        sda_i,
        output       sda_o,
        output       sda_oen
 
       );
 
 
 
        //
        // Variable declarations
        //
 
        // statemachine
        parameter [4:0] ST_IDLE  = 5'b0_0000;
        parameter [4:0] ST_START = 5'b0_0001;
        parameter [4:0] ST_READ  = 5'b0_0010;
        parameter [4:0] ST_WRITE = 5'b0_0100;
        parameter [4:0] ST_ACK   = 5'b0_1000;
        parameter [4:0] ST_STOP  = 5'b1_0000;
 
        // signals for bit_controller
        reg  [3:0] core_cmd;
        reg        core_txd;
        wire       core_ack, core_rxd;
 
        // signals for shift register
        reg [7:0] sr; //8bit shift register
        reg       shift, ld;
 
        // signals for state machine
        wire       go;
        reg  [2:0] dcnt;
        wire       cnt_done;
 
        //
        // Module body
        //
 
        // hookup bit_controller
        i2cm_bit_ctrl u_bit_ctrl (
                .clk     ( clk      ),
                .sresetn ( sresetn  ),
                .aresetn ( aresetn ),
                .ena     ( ena      ),
                .clk_cnt ( clk_cnt  ),
                .cmd     ( core_cmd ),
                .cmd_ack ( core_ack ),
                .busy    ( i2c_busy ),
                .al      ( i2c_al   ),
                .din     ( core_txd ),
                .dout    ( core_rxd ),
                .scl_i   ( scl_i    ),
                .scl_o   ( scl_o    ),
                .scl_oen ( scl_oen  ),
                .sda_i   ( sda_i    ),
                .sda_o   ( sda_o    ),
                .sda_oen ( sda_oen  )
        );
 
        // generate go-signal
        assign go = (read | write | stop) & ~cmd_ack;
 
        // assign dout output to shift-register
        assign dout = sr;
 
        // generate shift register
        always @(posedge clk or negedge aresetn)
          if (!aresetn)
            sr <= #1 8'h0;
          else if (!sresetn)
            sr <= #1 8'h0;
          else if (ld)
            sr <= #1 din;
          else if (shift)
            sr <= #1 {sr[6:0], core_rxd};
 
        // generate counter
        always @(posedge clk or negedge aresetn)
          if (!aresetn)
            dcnt <= #1 3'h0;
          else if (!sresetn)
            dcnt <= #1 3'h0;
          else if (ld)
            dcnt <= #1 3'h7;
          else if (shift)
            dcnt <= #1 dcnt - 3'h1;
 
        assign cnt_done = ~(|dcnt);
 
        //
        // state machine
        //
        reg [4:0] c_state; // synopsys enum_state
 
        always @(posedge clk or negedge aresetn)
          if (!aresetn)
            begin
                core_cmd <= #1 `I2C_CMD_NOP;
                core_txd <= #1 1'b0;
                shift    <= #1 1'b0;
                ld       <= #1 1'b0;
                cmd_ack  <= #1 1'b0;
                c_state  <= #1 ST_IDLE;
                ack_out  <= #1 1'b0;
            end
          else if (!sresetn | i2c_al)
           begin
               core_cmd <= #1 `I2C_CMD_NOP;
               core_txd <= #1 1'b0;
               shift    <= #1 1'b0;
               ld       <= #1 1'b0;
               cmd_ack  <= #1 1'b0;
               c_state  <= #1 ST_IDLE;
               ack_out  <= #1 1'b0;
           end
        else
          begin
              // initially reset all signals
              core_txd <= #1 sr[7];
              shift    <= #1 1'b0;
              ld       <= #1 1'b0;
              cmd_ack  <= #1 1'b0;
 
              case (c_state) // synopsys full_case parallel_case
                ST_IDLE:
                  if (go)
                    begin
                        if (start)
                          begin
                              c_state  <= #1 ST_START;
                              core_cmd <= #1 `I2C_CMD_START;
                          end
                        else if (read)
                          begin
                              c_state  <= #1 ST_READ;
                              core_cmd <= #1 `I2C_CMD_READ;
                          end
                        else if (write)
                          begin
                              c_state  <= #1 ST_WRITE;
                              core_cmd <= #1 `I2C_CMD_WRITE;
                          end
                        else // stop
                          begin
                              c_state  <= #1 ST_STOP;
                              core_cmd <= #1 `I2C_CMD_STOP;
                          end
 
                        ld <= #1 1'b1;
                    end
 
                ST_START:
                  if (core_ack)
                    begin
                        if (read)
                          begin
                              c_state  <= #1 ST_READ;
                              core_cmd <= #1 `I2C_CMD_READ;
                          end
                        else
                          begin
                              c_state  <= #1 ST_WRITE;
                              core_cmd <= #1 `I2C_CMD_WRITE;
                          end
 
                        ld <= #1 1'b1;
                    end
 
                ST_WRITE:
                  if (core_ack)
                    if (cnt_done)
                      begin
                          c_state  <= #1 ST_ACK;
                          core_cmd <= #1 `I2C_CMD_READ;
                      end
                    else
                      begin
                          c_state  <= #1 ST_WRITE;       // stay in same state
                          core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
                          shift    <= #1 1'b1;
                      end
 
                ST_READ:
                  if (core_ack)
                    begin
                        if (cnt_done)
                          begin
                              c_state  <= #1 ST_ACK;
                              core_cmd <= #1 `I2C_CMD_WRITE;
                          end
                        else
                          begin
                              c_state  <= #1 ST_READ;       // stay in same state
                              core_cmd <= #1 `I2C_CMD_READ; // read next bit
                          end
 
                        shift    <= #1 1'b1;
                        core_txd <= #1 ack_in;
                    end
 
                ST_ACK:
                  if (core_ack)
                    begin
                       if (stop)
                         begin
                             c_state  <= #1 ST_STOP;
                             core_cmd <= #1 `I2C_CMD_STOP;
                         end
                       else
                         begin
                             c_state  <= #1 ST_IDLE;
                             core_cmd <= #1 `I2C_CMD_NOP;
 
                             // generate command acknowledge signal
                             cmd_ack  <= #1 1'b1;
                         end
 
                         // assign ack_out output to bit_controller_rxd (contains last received bit)
                         ack_out <= #1 core_rxd;
 
                         core_txd <= #1 1'b1;
                     end
                   else
                     core_txd <= #1 ack_in;
 
                ST_STOP:
                  if (core_ack)
                    begin
                        c_state  <= #1 ST_IDLE;
                        core_cmd <= #1 `I2C_CMD_NOP;
 
                        // generate command acknowledge signal
                        cmd_ack  <= #1 1'b1;
                    end
 
              endcase
          end
endmodule

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[/] [oms8051mini/] [trunk/] [rtl/] [i2cm/] [i2cm_byte_ctrl.v] - Blame information for rev 28

Line No.	Rev	Author	Line
1	28	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OMS8051 I2C Master byte-controller Module ////`
4			`//// WISHBONE rev.B2 compliant I2C Master byte-controller ////`
5			`//// ////`
6			`//// This file is part of the OMS 8051 cores project ////`
7			`//// http://www.opencores.org/cores/oms8051mini/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// OMS 8051 definitions. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// -Richard Herveille , richard@asics.ws, www.asics.ws ////`
17			`//// -Dinesh Annayya, dinesha@opencores.org ////`
18			`//// ////`
19			`//// Revision : Jan 6, 2017 ////`
20			`//// ////`
21			`//////////////////////////////////////////////////////////////////////`
22			`// v0.0 - Dinesh A, 6th Jan 2017`
23			`// 1. Initail version picked from`
24			`// http://www.opencores.org/projects/i2c/`
25			`// 2. renaming of reset signal to aresetn and sresetn`
26			`//`
27			`//////////////////////////////////////////////////////////////////////`
28			`//// ////`
29			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
30			`//// ////`
31			`//// This source file may be used and distributed without ////`
32			`//// restriction provided that this copyright statement is not ////`
33			`//// removed from the file and that any derivative work contains ////`
34			`//// the original copyright notice and the associated disclaimer. ////`
35			`//// ////`
36			`//// This source file is free software; you can redistribute it ////`
37			`//// and/or modify it under the terms of the GNU Lesser General ////`
38			`//// Public License as published by the Free Software Foundation; ////`
39			`//// either version 2.1 of the License, or (at your option) any ////`
40			`//// later version. ////`
41			`//// ////`
42			`//// This source is distributed in the hope that it will be ////`
43			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
44			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
45			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
46			`//// details. ////`
47			`//// ////`
48			`//// You should have received a copy of the GNU Lesser General ////`
49			`//// Public License along with this source; if not, download it ////`
50			`//// from http://www.opencores.org/lgpl.shtml ////`
51			`//// ////`
52			`//////////////////////////////////////////////////////////////////////`
53
54			`include "i2cm_defines.v"
55
56			`module i2cm_byte_ctrl (`
57			`//`
58			`// inputs & outputs`
59			`//`
60			`input clk, // master clock`
61			`input sresetn, // synchronous active high reset`
62			`input aresetn, // asynchronous active low reset`
63			`input ena, // core enable signal`
64
65			`input [15:0] clk_cnt, // 4x SCL`
66
67			`// control inputs`
68			`input start,`
69			`input stop,`
70			`input read,`
71			`input write,`
72			`input ack_in,`
73			`input [7:0] din,`
74
75			`// status outputs`
76			`output reg cmd_ack,`
77			`output reg ack_out,`
78			`output i2c_busy,`
79			`output i2c_al,`
80			`output [7:0] dout,`
81
82			`// I2C signals`
83			`input scl_i,`
84			`output scl_o,`
85			`output scl_oen,`
86			`input sda_i,`
87			`output sda_o,`
88			`output sda_oen`
89
90			`);`
91
92
93
94			`//`
95			`// Variable declarations`
96			`//`
97
98			`// statemachine`
99			`parameter [4:0] ST_IDLE = 5'b0_0000;`
100			`parameter [4:0] ST_START = 5'b0_0001;`
101			`parameter [4:0] ST_READ = 5'b0_0010;`
102			`parameter [4:0] ST_WRITE = 5'b0_0100;`
103			`parameter [4:0] ST_ACK = 5'b0_1000;`
104			`parameter [4:0] ST_STOP = 5'b1_0000;`
105
106			`// signals for bit_controller`
107			`reg [3:0] core_cmd;`
108			`reg core_txd;`
109			`wire core_ack, core_rxd;`
110
111			`// signals for shift register`
112			`reg [7:0] sr; //8bit shift register`
113			`reg shift, ld;`
114
115			`// signals for state machine`
116			`wire go;`
117			`reg [2:0] dcnt;`
118			`wire cnt_done;`
119
120			`//`
121			`// Module body`
122			`//`
123
124			`// hookup bit_controller`
125			`i2cm_bit_ctrl u_bit_ctrl (`
126			`.clk ( clk ),`
127			`.sresetn ( sresetn ),`
128			`.aresetn ( aresetn ),`
129			`.ena ( ena ),`
130			`.clk_cnt ( clk_cnt ),`
131			`.cmd ( core_cmd ),`
132			`.cmd_ack ( core_ack ),`
133			`.busy ( i2c_busy ),`
134			`.al ( i2c_al ),`
135			`.din ( core_txd ),`
136			`.dout ( core_rxd ),`
137			`.scl_i ( scl_i ),`
138			`.scl_o ( scl_o ),`
139			`.scl_oen ( scl_oen ),`
140			`.sda_i ( sda_i ),`
141			`.sda_o ( sda_o ),`
142			`.sda_oen ( sda_oen )`
143			`);`
144
145			`// generate go-signal`
146			`assign go = (read \| write \| stop) & ~cmd_ack;`
147
148			`// assign dout output to shift-register`
149			`assign dout = sr;`
150
151			`// generate shift register`
152			`always @(posedge clk or negedge aresetn)`
153			`if (!aresetn)`
154			`sr <= #1 8'h0;`
155			`else if (!sresetn)`
156			`sr <= #1 8'h0;`
157			`else if (ld)`
158			`sr <= #1 din;`
159			`else if (shift)`
160			`sr <= #1 {sr[6:0], core_rxd};`
161
162			`// generate counter`
163			`always @(posedge clk or negedge aresetn)`
164			`if (!aresetn)`
165			`dcnt <= #1 3'h0;`
166			`else if (!sresetn)`
167			`dcnt <= #1 3'h0;`
168			`else if (ld)`
169			`dcnt <= #1 3'h7;`
170			`else if (shift)`
171			`dcnt <= #1 dcnt - 3'h1;`
172
173			`assign cnt_done = ~(\|dcnt);`
174
175			`//`
176			`// state machine`
177			`//`
178			`reg [4:0] c_state; // synopsys enum_state`
179
180			`always @(posedge clk or negedge aresetn)`
181			`if (!aresetn)`
182			`begin`
183			core_cmd <= #1 `I2C_CMD_NOP;
184			`core_txd <= #1 1'b0;`
185			`shift <= #1 1'b0;`
186			`ld <= #1 1'b0;`
187			`cmd_ack <= #1 1'b0;`
188			`c_state <= #1 ST_IDLE;`
189			`ack_out <= #1 1'b0;`
190			`end`
191			`else if (!sresetn \| i2c_al)`
192			`begin`
193			core_cmd <= #1 `I2C_CMD_NOP;
194			`core_txd <= #1 1'b0;`
195			`shift <= #1 1'b0;`
196			`ld <= #1 1'b0;`
197			`cmd_ack <= #1 1'b0;`
198			`c_state <= #1 ST_IDLE;`
199			`ack_out <= #1 1'b0;`
200			`end`
201			`else`
202			`begin`
203			`// initially reset all signals`
204			`core_txd <= #1 sr[7];`
205			`shift <= #1 1'b0;`
206			`ld <= #1 1'b0;`
207			`cmd_ack <= #1 1'b0;`
208
209			`case (c_state) // synopsys full_case parallel_case`
210			`ST_IDLE:`
211			`if (go)`
212			`begin`
213			`if (start)`
214			`begin`
215			`c_state <= #1 ST_START;`
216			core_cmd <= #1 `I2C_CMD_START;
217			`end`
218			`else if (read)`
219			`begin`
220			`c_state <= #1 ST_READ;`
221			core_cmd <= #1 `I2C_CMD_READ;
222			`end`
223			`else if (write)`
224			`begin`
225			`c_state <= #1 ST_WRITE;`
226			core_cmd <= #1 `I2C_CMD_WRITE;
227			`end`
228			`else // stop`
229			`begin`
230			`c_state <= #1 ST_STOP;`
231			core_cmd <= #1 `I2C_CMD_STOP;
232			`end`
233
234			`ld <= #1 1'b1;`
235			`end`
236
237			`ST_START:`
238			`if (core_ack)`
239			`begin`
240			`if (read)`
241			`begin`
242			`c_state <= #1 ST_READ;`
243			core_cmd <= #1 `I2C_CMD_READ;
244			`end`
245			`else`
246			`begin`
247			`c_state <= #1 ST_WRITE;`
248			core_cmd <= #1 `I2C_CMD_WRITE;
249			`end`
250
251			`ld <= #1 1'b1;`
252			`end`
253
254			`ST_WRITE:`
255			`if (core_ack)`
256			`if (cnt_done)`
257			`begin`
258			`c_state <= #1 ST_ACK;`
259			core_cmd <= #1 `I2C_CMD_READ;
260			`end`
261			`else`
262			`begin`
263			`c_state <= #1 ST_WRITE; // stay in same state`
264			core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
265			`shift <= #1 1'b1;`
266			`end`
267
268			`ST_READ:`
269			`if (core_ack)`
270			`begin`
271			`if (cnt_done)`
272			`begin`
273			`c_state <= #1 ST_ACK;`
274			core_cmd <= #1 `I2C_CMD_WRITE;
275			`end`
276			`else`
277			`begin`
278			`c_state <= #1 ST_READ; // stay in same state`
279			core_cmd <= #1 `I2C_CMD_READ; // read next bit
280			`end`
281
282			`shift <= #1 1'b1;`
283			`core_txd <= #1 ack_in;`
284			`end`
285
286			`ST_ACK:`
287			`if (core_ack)`
288			`begin`
289			`if (stop)`
290			`begin`
291			`c_state <= #1 ST_STOP;`
292			core_cmd <= #1 `I2C_CMD_STOP;
293			`end`
294			`else`
295			`begin`
296			`c_state <= #1 ST_IDLE;`
297			core_cmd <= #1 `I2C_CMD_NOP;
298
299			`// generate command acknowledge signal`
300			`cmd_ack <= #1 1'b1;`
301			`end`
302
303			`// assign ack_out output to bit_controller_rxd (contains last received bit)`
304			`ack_out <= #1 core_rxd;`
305
306			`core_txd <= #1 1'b1;`
307			`end`
308			`else`
309			`core_txd <= #1 ack_in;`
310
311			`ST_STOP:`
312			`if (core_ack)`
313			`begin`
314			`c_state <= #1 ST_IDLE;`
315			core_cmd <= #1 `I2C_CMD_NOP;
316
317			`// generate command acknowledge signal`
318			`cmd_ack <= #1 1'b1;`
319			`end`
320
321			`endcase`
322			`end`
323			`endmodule`