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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS8051 I2C Master Core Module                              ////
////  WISHBONE revB.2 compliant I2C Master controller Top-level   ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      -Richard Herveille ,  richard@asics.ws, www.asics.ws    ////
////      -Dinesh Annayya, dinesha@opencores.org                  ////
////                                                              ////
////  Revision : Jan 6, 2017                                      //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//     v0.0 - Dinesh A, 6th Jan 2017
//          1. Initail version picked from
//              http://www.opencores.org/projects/i2c/
//          2. renaming of reset signal to aresetn and sresetn
//
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "i2cm_defines.v"
 
module i2cm_top(
        // wishbone signals
        input        wb_clk_i,     // master clock input
        input        sresetn,      // synchronous reset
        input        aresetn,      // asynchronous reset
        input  [2:0] wb_adr_i,     // lower address bits
        input  [7:0] wb_dat_i,     // databus input
        output reg [7:0] wb_dat_o,     // databus output
        input        wb_we_i,      // write enable input
        input        wb_stb_i,     // stobe/core select signal
        input        wb_cyc_i,     // valid bus cycle input
        output reg   wb_ack_o,     // bus cycle acknowledge output
        output reg  wb_inta_o,    // interrupt request signal output
 
        // I2C signals
        // i2c clock line
        input        scl_pad_i,    // SCL-line input
        output       scl_pad_o,    // SCL-line output (always 1'b0)
        output       scl_padoen_o, // SCL-line output enable (active low)
 
        // i2c data line
        input        sda_pad_i,    // SDA-line input
        output       sda_pad_o,    // SDA-line output (always 1'b0)
        output       sda_padoen_o  // SDA-line output enable (active low)
 
         );
 
 
        //
        // variable declarations
        //
 
        // registers
        reg  [15:0] prer; // clock prescale register
        reg  [ 7:0] ctr;  // control register
        reg  [ 7:0] txr;  // transmit register
        wire [ 7:0] rxr;  // receive register
        reg  [ 7:0] cr;   // command register
        wire [ 7:0] sr;   // status register
 
        // done signal: command completed, clear command register
        wire done;
 
        // core enable signal
        wire core_en;
        wire ien;
 
        // status register signals
        wire irxack;
        reg  rxack;       // received aknowledge from slave
        reg  tip;         // transfer in progress
        reg  irq_flag;    // interrupt pending flag
        wire i2c_busy;    // bus busy (start signal detected)
        wire i2c_al;      // i2c bus arbitration lost
        reg  al;          // status register arbitration lost bit
 
        //
        // module body
        //
 
 
        // generate wishbone signals
        wire wb_wacc = wb_we_i & wb_ack_o;
 
        // generate acknowledge output signal
        always @(posedge wb_clk_i)
          wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
 
        // assign DAT_O
        always @(posedge wb_clk_i)
        begin
          case (wb_adr_i) // synopsys parallel_case
            3'b000: wb_dat_o <= #1 prer[ 7:0];
            3'b001: wb_dat_o <= #1 prer[15:8];
            3'b010: wb_dat_o <= #1 ctr;
            3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
            3'b100: wb_dat_o <= #1 sr;  // write is command register (cr)
            3'b101: wb_dat_o <= #1 txr;
            3'b110: wb_dat_o <= #1 cr;
            3'b111: wb_dat_o <= #1 0;   // reserved
          endcase
        end
 
        // generate registers
        always @(posedge wb_clk_i or negedge aresetn)
          if (!aresetn)
            begin
                prer <= #1 16'hffff;
                ctr  <= #1  8'h0;
                txr  <= #1  8'h0;
            end
          else if (!sresetn)
            begin
                prer <= #1 16'hffff;
                ctr  <= #1  8'h0;
                txr  <= #1  8'h0;
            end
          else
            if (wb_wacc)
              case (wb_adr_i) // synopsys parallel_case
                 3'b000 : prer [ 7:0] <= #1 wb_dat_i;
                 3'b001 : prer [15:8] <= #1 wb_dat_i;
                 3'b010 : ctr         <= #1 wb_dat_i;
                 3'b011 : txr         <= #1 wb_dat_i;
                 default: ;
              endcase
 
        // generate command register (special case)
        always @(posedge wb_clk_i or negedge aresetn)
          if (!aresetn)
            cr <= #1 8'h0;
          else if (!sresetn)
            cr <= #1 8'h0;
          else if (wb_wacc)
            begin
                if (core_en & (wb_adr_i == 3'b100) )
                  cr <= #1 wb_dat_i;
            end
          else
            begin
                if (done | i2c_al)
                  cr[7:4] <= #1 4'h0;           // clear command bits when done
                                                // or when aribitration lost
                cr[2:1] <= #1 2'b0;             // reserved bits
                cr[0]   <= #1 1'b0;             // clear IRQ_ACK bit
            end
 
 
        // decode command register
        wire sta  = cr[7];
        wire sto  = cr[6];
        wire rd   = cr[5];
        wire wr   = cr[4];
        wire ack  = cr[3];
        wire iack = cr[0];
 
        // decode control register
        assign core_en = ctr[7];
        assign ien = ctr[6];
 
        // hookup byte controller block
        i2cm_byte_ctrl u_byte_ctrl (
                .clk      ( wb_clk_i     ),
                .sresetn  ( sresetn      ),
                .aresetn  ( aresetn      ),
                .ena      ( core_en      ),
                .clk_cnt  ( prer         ),
                .start    ( sta          ),
                .stop     ( sto          ),
                .read     ( rd           ),
                .write    ( wr           ),
                .ack_in   ( ack          ),
                .din      ( txr          ),
                .cmd_ack  ( done         ),
                .ack_out  ( irxack       ),
                .dout     ( rxr          ),
                .i2c_busy ( i2c_busy     ),
                .i2c_al   ( i2c_al       ),
                .scl_i    ( scl_pad_i    ),
                .scl_o    ( scl_pad_o    ),
                .scl_oen  ( scl_padoen_o ),
                .sda_i    ( sda_pad_i    ),
                .sda_o    ( sda_pad_o    ),
                .sda_oen  ( sda_padoen_o )
        );
 
        // status register block + interrupt request signal
        always @(posedge wb_clk_i or negedge aresetn)
          if (!aresetn)
            begin
                al       <= #1 1'b0;
                rxack    <= #1 1'b0;
                tip      <= #1 1'b0;
                irq_flag <= #1 1'b0;
            end
          else if (!sresetn)
            begin
                al       <= #1 1'b0;
                rxack    <= #1 1'b0;
                tip      <= #1 1'b0;
                irq_flag <= #1 1'b0;
            end
          else
            begin
                al       <= #1 i2c_al | (al & ~sta);
                rxack    <= #1 irxack;
                tip      <= #1 (rd | wr);
                irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
            end
 
        // generate interrupt request signals
        always @(posedge wb_clk_i or negedge aresetn)
          if (!aresetn)
            wb_inta_o <= #1 1'b0;
          else if (!sresetn)
            wb_inta_o <= #1 1'b0;
          else
            wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
 
        // assign status register bits
        assign sr[7]   = rxack;
        assign sr[6]   = i2c_busy;
        assign sr[5]   = al;
        assign sr[4:2] = 3'h0; // reserved
        assign sr[1]   = tip;
        assign sr[0]   = irq_flag;
 
endmodule

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[/] [oms8051mini/] [trunk/] [rtl/] [i2cm/] [i2cm_top.v] - Blame information for rev 32

Line No.	Rev	Author	Line
1	28	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OMS8051 I2C Master Core Module ////`
4			`//// WISHBONE revB.2 compliant I2C Master controller Top-level ////`
5			`//// ////`
6			`//// This file is part of the OMS 8051 cores project ////`
7			`//// http://www.opencores.org/cores/oms8051mini/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// OMS 8051 definitions. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// -Richard Herveille , richard@asics.ws, www.asics.ws ////`
17			`//// -Dinesh Annayya, dinesha@opencores.org ////`
18			`//// ////`
19			`//// Revision : Jan 6, 2017 ////`
20			`//// ////`
21			`//////////////////////////////////////////////////////////////////////`
22			`// v0.0 - Dinesh A, 6th Jan 2017`
23			`// 1. Initail version picked from`
24			`// http://www.opencores.org/projects/i2c/`
25			`// 2. renaming of reset signal to aresetn and sresetn`
26			`//`
27			`//////////////////////////////////////////////////////////////////////`
28			`//// ////`
29			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
30			`//// ////`
31			`//// This source file may be used and distributed without ////`
32			`//// restriction provided that this copyright statement is not ////`
33			`//// removed from the file and that any derivative work contains ////`
34			`//// the original copyright notice and the associated disclaimer. ////`
35			`//// ////`
36			`//// This source file is free software; you can redistribute it ////`
37			`//// and/or modify it under the terms of the GNU Lesser General ////`
38			`//// Public License as published by the Free Software Foundation; ////`
39			`//// either version 2.1 of the License, or (at your option) any ////`
40			`//// later version. ////`
41			`//// ////`
42			`//// This source is distributed in the hope that it will be ////`
43			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
44			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
45			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
46			`//// details. ////`
47			`//// ////`
48			`//// You should have received a copy of the GNU Lesser General ////`
49			`//// Public License along with this source; if not, download it ////`
50			`//// from http://www.opencores.org/lgpl.shtml ////`
51			`//// ////`
52			`//////////////////////////////////////////////////////////////////////`
53
54			`include "i2cm_defines.v"
55
56			`module i2cm_top(`
57			`// wishbone signals`
58			`input wb_clk_i, // master clock input`
59			`input sresetn, // synchronous reset`
60			`input aresetn, // asynchronous reset`
61			`input [2:0] wb_adr_i, // lower address bits`
62			`input [7:0] wb_dat_i, // databus input`
63			`output reg [7:0] wb_dat_o, // databus output`
64			`input wb_we_i, // write enable input`
65			`input wb_stb_i, // stobe/core select signal`
66			`input wb_cyc_i, // valid bus cycle input`
67			`output reg wb_ack_o, // bus cycle acknowledge output`
68			`output reg wb_inta_o, // interrupt request signal output`
69
70			`// I2C signals`
71			`// i2c clock line`
72			`input scl_pad_i, // SCL-line input`
73			`output scl_pad_o, // SCL-line output (always 1'b0)`
74			`output scl_padoen_o, // SCL-line output enable (active low)`
75
76			`// i2c data line`
77			`input sda_pad_i, // SDA-line input`
78			`output sda_pad_o, // SDA-line output (always 1'b0)`
79			`output sda_padoen_o // SDA-line output enable (active low)`
80
81			`);`
82
83
84			`//`
85			`// variable declarations`
86			`//`
87
88			`// registers`
89			`reg [15:0] prer; // clock prescale register`
90			`reg [ 7:0] ctr; // control register`
91			`reg [ 7:0] txr; // transmit register`
92			`wire [ 7:0] rxr; // receive register`
93			`reg [ 7:0] cr; // command register`
94			`wire [ 7:0] sr; // status register`
95
96			`// done signal: command completed, clear command register`
97			`wire done;`
98
99			`// core enable signal`
100			`wire core_en;`
101			`wire ien;`
102
103			`// status register signals`
104			`wire irxack;`
105			`reg rxack; // received aknowledge from slave`
106			`reg tip; // transfer in progress`
107			`reg irq_flag; // interrupt pending flag`
108			`wire i2c_busy; // bus busy (start signal detected)`
109			`wire i2c_al; // i2c bus arbitration lost`
110			`reg al; // status register arbitration lost bit`
111
112			`//`
113			`// module body`
114			`//`
115
116
117			`// generate wishbone signals`
118			`wire wb_wacc = wb_we_i & wb_ack_o;`
119
120			`// generate acknowledge output signal`
121			`always @(posedge wb_clk_i)`
122			`wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored`
123
124			`// assign DAT_O`
125			`always @(posedge wb_clk_i)`
126			`begin`
127			`case (wb_adr_i) // synopsys parallel_case`
128			`3'b000: wb_dat_o <= #1 prer[ 7:0];`
129			`3'b001: wb_dat_o <= #1 prer[15:8];`
130			`3'b010: wb_dat_o <= #1 ctr;`
131			`3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)`
132			`3'b100: wb_dat_o <= #1 sr; // write is command register (cr)`
133			`3'b101: wb_dat_o <= #1 txr;`
134			`3'b110: wb_dat_o <= #1 cr;`
135			`3'b111: wb_dat_o <= #1 0; // reserved`
136			`endcase`
137			`end`
138
139			`// generate registers`
140			`always @(posedge wb_clk_i or negedge aresetn)`
141			`if (!aresetn)`
142			`begin`
143			`prer <= #1 16'hffff;`
144			`ctr <= #1 8'h0;`
145			`txr <= #1 8'h0;`
146			`end`
147			`else if (!sresetn)`
148			`begin`
149			`prer <= #1 16'hffff;`
150			`ctr <= #1 8'h0;`
151			`txr <= #1 8'h0;`
152			`end`
153			`else`
154			`if (wb_wacc)`
155			`case (wb_adr_i) // synopsys parallel_case`
156			`3'b000 : prer [ 7:0] <= #1 wb_dat_i;`
157			`3'b001 : prer [15:8] <= #1 wb_dat_i;`
158			`3'b010 : ctr <= #1 wb_dat_i;`
159			`3'b011 : txr <= #1 wb_dat_i;`
160			`default: ;`
161			`endcase`
162
163			`// generate command register (special case)`
164			`always @(posedge wb_clk_i or negedge aresetn)`
165			`if (!aresetn)`
166			`cr <= #1 8'h0;`
167			`else if (!sresetn)`
168			`cr <= #1 8'h0;`
169			`else if (wb_wacc)`
170			`begin`
171			`if (core_en & (wb_adr_i == 3'b100) )`
172			`cr <= #1 wb_dat_i;`
173			`end`
174			`else`
175			`begin`
176			`if (done \| i2c_al)`
177			`cr[7:4] <= #1 4'h0; // clear command bits when done`
178			`// or when aribitration lost`
179			`cr[2:1] <= #1 2'b0; // reserved bits`
180			`cr[0] <= #1 1'b0; // clear IRQ_ACK bit`
181			`end`
182
183
184			`// decode command register`
185			`wire sta = cr[7];`
186			`wire sto = cr[6];`
187			`wire rd = cr[5];`
188			`wire wr = cr[4];`
189			`wire ack = cr[3];`
190			`wire iack = cr[0];`
191
192			`// decode control register`
193			`assign core_en = ctr[7];`
194			`assign ien = ctr[6];`
195
196			`// hookup byte controller block`
197			`i2cm_byte_ctrl u_byte_ctrl (`
198			`.clk ( wb_clk_i ),`
199			`.sresetn ( sresetn ),`
200			`.aresetn ( aresetn ),`
201			`.ena ( core_en ),`
202			`.clk_cnt ( prer ),`
203			`.start ( sta ),`
204			`.stop ( sto ),`
205			`.read ( rd ),`
206			`.write ( wr ),`
207			`.ack_in ( ack ),`
208			`.din ( txr ),`
209			`.cmd_ack ( done ),`
210			`.ack_out ( irxack ),`
211			`.dout ( rxr ),`
212			`.i2c_busy ( i2c_busy ),`
213			`.i2c_al ( i2c_al ),`
214			`.scl_i ( scl_pad_i ),`
215			`.scl_o ( scl_pad_o ),`
216			`.scl_oen ( scl_padoen_o ),`
217			`.sda_i ( sda_pad_i ),`
218			`.sda_o ( sda_pad_o ),`
219			`.sda_oen ( sda_padoen_o )`
220			`);`
221
222			`// status register block + interrupt request signal`
223			`always @(posedge wb_clk_i or negedge aresetn)`
224			`if (!aresetn)`
225			`begin`
226			`al <= #1 1'b0;`
227			`rxack <= #1 1'b0;`
228			`tip <= #1 1'b0;`
229			`irq_flag <= #1 1'b0;`
230			`end`
231			`else if (!sresetn)`
232			`begin`
233			`al <= #1 1'b0;`
234			`rxack <= #1 1'b0;`
235			`tip <= #1 1'b0;`
236			`irq_flag <= #1 1'b0;`
237			`end`
238			`else`
239			`begin`
240			`al <= #1 i2c_al \| (al & ~sta);`
241			`rxack <= #1 irxack;`
242			`tip <= #1 (rd \| wr);`
243			`irq_flag <= #1 (done \| i2c_al \| irq_flag) & ~iack; // interrupt request flag is always generated`
244			`end`
245
246			`// generate interrupt request signals`
247			`always @(posedge wb_clk_i or negedge aresetn)`
248			`if (!aresetn)`
249			`wb_inta_o <= #1 1'b0;`
250			`else if (!sresetn)`
251			`wb_inta_o <= #1 1'b0;`
252			`else`
253			`wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)`
254
255			`// assign status register bits`
256			`assign sr[7] = rxack;`
257			`assign sr[6] = i2c_busy;`
258			`assign sr[5] = al;`
259			`assign sr[4:2] = 3'h0; // reserved`
260			`assign sr[1] = tip;`
261			`assign sr[0] = irq_flag;`
262
263			`endmodule`