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dinesha |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// OMS 8051 cores common library Module ////
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//// ////
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//// This file is part of the OMS 8051 cores project ////
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//// http://www.opencores.org/cores/oms8051mini/ ////
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//// ////
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//// Description ////
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//// OMS 8051 definitions. ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// Revision : Nov 26, 2016 ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// #################################################################
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// Module: clk_ctl
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//
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// Description: Generic clock control logic , clk-out = mclk/(2+clk_div_ratio)
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//
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//
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// #################################################################
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module clk_ctl (
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// Outputs
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clk_o,
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// Inputs
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mclk,
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reset_n,
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clk_div_ratio
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);
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//---------------------------------
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// CLOCK Default Divider value.
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// This value will be change from outside
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//---------------------------------
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parameter WD = 'h1;
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//---------------------------------------------
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// All the input to this block are declared here
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// --------------------------------------------
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input mclk ;//
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input reset_n ;// primary reset signal
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input [WD:0] clk_div_ratio ;// primary clock divide ratio
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// output clock = selected clock / (div_ratio+1)
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//---------------------------------------------
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// All the output to this block are declared here
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// --------------------------------------------
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output clk_o ; // clock out
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//------------------------------------
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// Clock Divide func is done here
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//------------------------------------
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reg [WD-1:0] high_count ; // high level counter
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reg [WD-1:0] low_count ; // low level counter
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reg mclk_div ; // divided clock
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assign clk_o = mclk_div;
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always @ (posedge mclk or negedge reset_n)
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begin // {
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if(reset_n == 1'b0)
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begin
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high_count <= 'h0;
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low_count <= 'h0;
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mclk_div <= 'b0;
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end
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else
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begin
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if(high_count != 0)
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begin // {
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high_count <= high_count - 1;
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mclk_div <= 1'b1;
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end // }
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else if(low_count != 0)
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begin // {
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low_count <= low_count - 1;
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mclk_div <= 1'b0;
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end // }
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else
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begin // {
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high_count <= clk_div_ratio[WD:1] + clk_div_ratio[0];
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low_count <= clk_div_ratio[WD:1] + 1;
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mclk_div <= ~mclk_div;
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end // }
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end // }
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end // }
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endmodule
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