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1 2 dinesha
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OMS 8051 cores common library Module                        ////
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////                                                              ////
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////  This file is part of the OMS 8051 cores project             ////
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////  http://www.opencores.org/cores/oms8051mini/                 ////
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////                                                              ////
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////  Description                                                 ////
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////  OMS 8051 definitions.                                       ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
18 36 dinesha
////  Revision : Nov 26, 2016                                    
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////      v-0.0 - Dinesh.A, Nov 26, 2016
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////          1. Initial Version
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////      v-0.1 - Dinesh.A, Jan 19, 2017
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////          1. Lint warning fixes, Seperated resetable and non 
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//               resetable logic                        
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//////////////////////////////////////////////////////////////////////
25 2 dinesha
////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
50
 
51
/**********************************************
52
      Web-bone cross bar M-Master By S-Slave
53
**********************************************/
54
 
55
module wb_crossbar (
56
 
57
              rst_n               ,
58
              clk                 ,
59
 
60
 
61
    // Master Interface Signal
62
              wbd_taddr_master    ,
63
              wbd_din_master      ,
64
              wbd_dout_master     ,
65
              wbd_adr_master      ,
66
              wbd_be_master       ,
67
              wbd_we_master       ,
68
              wbd_ack_master      ,
69
              wbd_stb_master      ,
70
              wbd_cyc_master      ,
71
              wbd_err_master      ,
72
              wbd_rty_master      ,
73
 
74
    // Slave Interface Signal
75
              wbd_din_slave       ,
76
              wbd_dout_slave      ,
77
              wbd_adr_slave       ,
78
              wbd_be_slave        ,
79
              wbd_we_slave        ,
80
              wbd_ack_slave       ,
81
              wbd_stb_slave       ,
82
              wbd_cyc_slave       ,
83
              wbd_err_slave       ,
84
              wbd_rty_slave
85
         );
86
 
87
parameter WB_SLAVE   = 4 ;
88
parameter WB_MASTER  = 4 ;
89
 
90
parameter D_WD    = 16; // Data Width
91
parameter BE_WD   = 2;  // Byte Enable
92
parameter ADR_WD  = 28; // Address Width
93
parameter TAR_WD  = 4;  // Target Width
94
 
95
input                  clk; // CLK_I The clock input [CLK_I] coordinates all activities 
96
                            // for the internal logic within the WISHBONE interconnect. 
97
                            // All WISHBONE output signals are registered at the 
98
                            // rising edge of [CLK_I]. 
99
                            // All WISHBONE input signals must be stable before the 
100
                            // rising edge of [CLK_I]. 
101
input                  rst_n; // RST_I The reset input [RST_I] forces the WISHBONE interface 
102
                            // to restart. Furthermore, all internal self-starting state 
103
                            // machines will be forced into an initial state. 
104
 
105
input [(WB_MASTER *TAR_WD)-1:0] wbd_taddr_master; // target address from master 
106
input [WB_MASTER-1:0]  wbd_stb_master;
107
                    // STB_O The strobe output [STB_O] indicates a valid data 
108
                    // transfer cycle. It is used to qualify various other signals 
109
                    // on the interface such as [SEL_O(7..0)]. The SLAVE must 
110
                    // assert either the [ACK_I], [ERR_I] or [RTY_I] signals in 
111
                    // response to every assertion of the [STB_O] signal. 
112
output [WB_SLAVE-1:0]  wbd_stb_slave;
113
                    // STB_O The strobe output [STB_O] indicates a valid data 
114
                    // transfer cycle. It is used to qualify various other signals 
115
                    // on the interface such as [SEL_O(7..0)]. The SLAVE must 
116
                    // assert either the [ACK_I], [ERR_I] or [RTY_I] signals in 
117
                    // response to every assertion of the [STB_O] signal. 
118
 
119
input [WB_MASTER-1:0]   wbd_we_master;
120
                    // WE_O The write enable output [WE_O] indicates whether the 
121
                    // current local bus cycle is a READ or WRITE cycle. The 
122
                    // signal is negated during READ cycles, and is asserted 
123
                    // during WRITE cycles. 
124
output [WB_SLAVE-1:0]   wbd_we_slave;
125
                    // WE_O The write enable output [WE_O] indicates whether the 
126
                    // current local bus cycle is a READ or WRITE cycle. The 
127
                    // signal is negated during READ cycles, and is asserted 
128
                    // during WRITE cycles. 
129
 
130
output [WB_MASTER-1:0]  wbd_ack_master;
131
                    // The acknowledge input [ACK_I], when asserted, 
132
                    // indicates the termination of a normal bus cycle. 
133
                    // Also see the [ERR_I] and [RTY_I] signal descriptions. 
134
input [WB_SLAVE-1:0]  wbd_ack_slave;
135
                    // The acknowledge input [ACK_I], when asserted, 
136
                    // indicates the termination of a normal bus cycle. 
137
                    // Also see the [ERR_I] and [RTY_I] signal descriptions. 
138
 
139
input [(WB_MASTER *ADR_WD)-1:0] wbd_adr_master;
140
                    // The address output array [ADR_O(63..0)] is used 
141
                    // to pass a binary address, with the most significant 
142
                    // address bit at the higher numbered end of the signal array. 
143
                    // The lower array boundary is specific to the data port size. 
144
                    // The higher array boundary is core-specific. 
145
                    // In some cases (such as FIFO interfaces) 
146
                    // the array may not be present on the interface. 
147
 
148
output [(WB_SLAVE *ADR_WD)-1:0] wbd_adr_slave;
149
                    // The address output array [ADR_O(63..0)] is used 
150
                    // to pass a binary address, with the most significant 
151
                    // address bit at the higher numbered end of the signal array. 
152
                    // The lower array boundary is specific to the data port size. 
153
                    // The higher array boundary is core-specific. 
154
                    // In some cases (such as FIFO interfaces) 
155
                    // the array may not be present on the interface. 
156
 
157
input [(WB_MASTER * BE_WD)-1:0] wbd_be_master; // Byte Enable 
158
                    // SEL_O(7..0) The select output array [SEL_O(7..0)] indicates 
159
                    // where valid data is expected on the [DAT_I(63..0)] signal 
160
                    // array during READ cycles, and where it is placed on the 
161
                    // [DAT_O(63..0)] signal array during WRITE cycles. 
162
                    // Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O] 
163
                    // signal descriptions.
164
output [(WB_SLAVE * BE_WD)-1:0] wbd_be_slave; // Byte Enable  
165
                    // SEL_O(7..0) The select output array [SEL_O(7..0)] indicates 
166
                    // where valid data is expected on the [DAT_I(63..0)] signal 
167
                    // array during READ cycles, and where it is placed on the 
168
                    // [DAT_O(63..0)] signal array during WRITE cycles. 
169
                    // Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O] 
170
                    // signal descriptions.
171
 
172
input [WB_MASTER -1:0] wbd_cyc_master;
173
                    // CYC_O The cycle output [CYC_O], when asserted, 
174
                    // indicates that a valid bus cycle is in progress. 
175
                    // The signal is asserted for the duration of all bus cycles. 
176
                    // For example, during a BLOCK transfer cycle there can be 
177
                    // multiple data transfers. The [CYC_O] signal is asserted 
178
                    // during the first data transfer, and remains asserted 
179
                    // until the last data transfer. The [CYC_O] signal is useful 
180
                    // for interfaces with multi-port interfaces 
181
                    // (such as dual port memories). In these cases, 
182
                    // the [CYC_O] signal requests use of a common bus from an 
183
                    // arbiter. Once the arbiter grants the bus to the MASTER, 
184
                    // it is held until [CYC_O] is negated. 
185
output [WB_SLAVE -1:0] wbd_cyc_slave;
186
                    // CYC_O The cycle output [CYC_O], when asserted, 
187
                    // indicates that a valid bus cycle is in progress. 
188
                    // The signal is asserted for the duration of all bus cycles. 
189
                    // For example, during a BLOCK transfer cycle there can be 
190
                    // multiple data transfers. The [CYC_O] signal is asserted 
191
                    // during the first data transfer, and remains asserted 
192
                    // until the last data transfer. The [CYC_O] signal is useful 
193
                    // for interfaces with multi-port interfaces 
194
                    // (such as dual port memories). In these cases, 
195
                    // the [CYC_O] signal requests use of a common bus from an 
196
                    // arbiter. Once the arbiter grants the bus to the MASTER, 
197
                    // it is held until [CYC_O] is negated. 
198
 
199
input [(WB_MASTER * D_WD)-1:0] wbd_din_master;
200
                    // DAT_I(63..0) The data input array [DAT_I(63..0)] is 
201
                    // used to pass binary data. The array boundaries are 
202
                    // determined by the port size. Also see the [DAT_O(63..0)] 
203
                    // and [SEL_O(7..0)] signal descriptions. 
204
 
205
output [(WB_SLAVE * D_WD)-1:0] wbd_din_slave;
206
                    // DAT_I(63..0) The data input array [DAT_I(63..0)] is 
207
                    // used to pass binary data. The array boundaries are 
208
                    // determined by the port size. Also see the [DAT_O(63..0)] 
209
                    // and [SEL_O(7..0)] signal descriptions. 
210
 
211
output [(WB_MASTER * D_WD)-1:0] wbd_dout_master;
212
                    // DAT_O(63..0) The data output array [DAT_O(63..0)] is 
213
                    // used to pass binary data. The array boundaries are 
214
                    // determined by the port size. Also see the [DAT_I(63..0)] 
215
                         // and [SEL_O(7..0)] signal descriptions. 
216
input [(WB_SLAVE * D_WD)-1:0] wbd_dout_slave;
217
                    // DAT_O(63..0) The data output array [DAT_O(63..0)] is 
218
                    // used to pass binary data. The array boundaries are 
219
                    // determined by the port size. Also see the [DAT_I(63..0)] 
220
                    // and [SEL_O(7..0)] signal descriptions. 
221
 
222
output [WB_MASTER -1:0]  wbd_err_master;
223
                    // ERR_I The error input [ERR_I] indicates an abnormal 
224
                    // cycle termination. The source of the error, and the 
225
                    // response generated by the MASTER is defined by the IP core 
226
                    // supplier in the WISHBONE DATASHEET. Also see the [ACK_I] 
227
                    // and [RTY_I] signal descriptions. 
228
input [WB_SLAVE -1:0]  wbd_err_slave;
229
                    // ERR_I The error input [ERR_I] indicates an abnormal 
230
                    // cycle termination. The source of the error, and the 
231
                    // response generated by the MASTER is defined by the IP core 
232
                    // supplier in the WISHBONE DATASHEET. Also see the [ACK_I] 
233
                    // and [RTY_I] signal descriptions. 
234
 
235
output [WB_MASTER -1:0]   wbd_rty_master;
236
                    // RTY_I The retry input [RTY_I] indicates that the indicates 
237
                    // that the interface is not ready to accept or send data, and 
238
                    // that the cycle should be retried. When and how the cycle is 
239
                    // retried is defined by the IP core supplier in the WISHBONE 
240
                    // DATASHEET. Also see the [ERR_I] and [RTY_I] signal 
241
                    // descriptions. 
242
input [WB_SLAVE -1:0]   wbd_rty_slave;
243
                    // RTY_I The retry input [RTY_I] indicates that the indicates 
244
                    // that the interface is not ready to accept or send data, and 
245
                    // that the cycle should be retried. When and how the cycle is 
246
                    // retried is defined by the IP core supplier in the WISHBONE 
247
                    // DATASHEET. Also see the [ERR_I] and [RTY_I] signal 
248
                    // descriptions. 
249
 
250
 
251
reg  [WB_MASTER-1:0]  wbd_ack_master;
252
reg  [WB_MASTER-1:0]  wbd_err_master;
253
reg  [WB_MASTER-1:0]  wbd_rty_master;
254
 
255
 
256
reg  [WB_MASTER-1:0]  master_busy; // master busy flag
257
reg  [WB_SLAVE-1:0]   slave_busy;  // slave busy flag
258
reg  [TAR_WD -1:0]     master_mx_id[WB_MASTER-1:0];
259
reg  [TAR_WD -1:0]     slave_mx_id [WB_SLAVE-1:0];
260
 
261 10 dinesha
wire  [TAR_WD-1:0]     wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master 
262 2 dinesha
wire  [D_WD-1:0]       wbd_din_master_t[WB_MASTER-1:0]; // target address from master 
263
reg   [D_WD-1:0]       wbd_dout_master_t[WB_MASTER-1:0]; // target address from master 
264
wire  [ADR_WD-1:0]     wbd_adr_master_t[WB_MASTER-1:0]; // target address from master 
265
wire  [BE_WD-1:0]      wbd_be_master_t[WB_MASTER-1:0]; // target address from master 
266
 
267
 
268
reg  [WB_SLAVE-1:0]  wbd_stb_slave;
269
reg  [WB_SLAVE-1:0]  wbd_we_slave;
270
reg  [WB_SLAVE-1:0]  wbd_cyc_slave;
271
wire [D_WD-1:0]      wbd_dout_slave_t[WB_SLAVE-1:0]; // target data towards master 
272
 
273
 
274
reg   [D_WD-1:0]     wbd_din_slave_t[WB_SLAVE-1:0]; // target address from master 
275
reg   [ADR_WD-1:0]    wbd_adr_slave_t[WB_SLAVE-1:0]; // target address from master 
276
reg   [BE_WD-1:0]     wbd_be_slave_t[WB_SLAVE-1:0]; // target address from master 
277
 
278 36 dinesha
integer i,k,l,n;
279 2 dinesha
 
280
 
281
/**********************************************************
282
   Re-Arraging the array in seperate two dimensional information
283
***********************************************************/
284
 
285
genvar j,m;
286
generate
287
 
288
  // Connect the Master Mux
289
  for(j=0; j < WB_MASTER ; j = j + 1) begin : master_expand
290
     assign wbd_taddr_master_t[j] = wbd_taddr_master[((j+1)*TAR_WD)-1:j * TAR_WD];
291
     assign wbd_din_master_t[j]  = wbd_din_master[((j+1)*D_WD)-1:j * D_WD];
292
     assign wbd_adr_master_t[j]  = wbd_adr_master[((j+1)*ADR_WD)-1:j * ADR_WD];
293
     assign wbd_be_master_t[j]   = wbd_be_master[((j+1)*BE_WD)-1:j * BE_WD];
294
 
295
     assign wbd_dout_master[((j+1)*D_WD)-1:j * D_WD] = wbd_dout_master_t[j];
296
  end
297
 
298
  // Connect the Slave Mux
299
  for(m=0; m < WB_SLAVE ; m = m + 1) begin : slave_expand
300
     assign wbd_din_slave[((m+1)*D_WD)-1:m * D_WD]        = wbd_din_slave_t[m];
301
     assign wbd_adr_slave[((m+1)*ADR_WD)-1:m * ADR_WD]   = wbd_adr_slave_t[m];
302
     assign wbd_be_slave[((m+1)*BE_WD)-1:m * BE_WD]      = wbd_be_slave_t[m];
303
 
304
     assign wbd_dout_slave_t[m]   = wbd_dout_slave[((m+1)*D_WD)-1:m * D_WD];
305
 
306
  end
307
endgenerate
308
 
309
always @*   begin
310
   for(k = 0; k < WB_MASTER; k = k + 1) begin
311
      if(master_busy[k] == 1) begin
312
         wbd_dout_master_t[k] = wbd_dout_slave_t[master_mx_id[k]];
313
         wbd_ack_master[k]    = wbd_ack_slave[master_mx_id[k]];
314
         wbd_err_master[k]    = wbd_err_slave[master_mx_id[k]];
315
         wbd_rty_master[k]    = wbd_rty_slave[master_mx_id[k]];
316
      end else begin
317
         wbd_dout_master_t[k] = 0;
318
         wbd_ack_master[k]    = 0;
319
         wbd_err_master[k]    = 0;
320
         wbd_rty_master[k]    = 0;
321
      end
322
   end
323
   for(l = 0; l < WB_SLAVE; l = l + 1) begin
324
      if(slave_busy[l] == 1) begin
325
         wbd_din_slave_t[l]  = wbd_din_master_t[slave_mx_id[l]];
326
         wbd_adr_slave_t[l]  = wbd_adr_master_t[slave_mx_id[l]];
327
         wbd_be_slave_t[l]   = wbd_be_master_t[slave_mx_id[l]];
328
         wbd_stb_slave[l]    = wbd_stb_master[slave_mx_id[l]];
329
         wbd_we_slave[l]     = wbd_we_master[slave_mx_id[l]];
330
         wbd_cyc_slave[l]    = wbd_cyc_master[slave_mx_id[l]];
331
      end else begin
332
         wbd_din_slave_t[l]  = 0;
333
         wbd_adr_slave_t[l]  = 0;
334
         wbd_be_slave_t[l]   = 0;
335
         wbd_stb_slave[l]    = 0;
336
         wbd_we_slave[l]     = 0;
337
         wbd_cyc_slave[l]    = 0;
338
      end
339
   end
340
end
341
 
342
/*******************************************************
343
   Parsing through the master and deciding on mux connectio
344
   Step-1: analysis the master from 0 to total master
345
   Step-2: If the previously master is not busy,
346
           Then check for any new request from the master and
347
           check corresponding slave is free or not. If there is
348
           master request and requesting slave is free.
349
           Then set the master max id to slave id &
350
           requesting slave to master number & set the master
351
           and slave busy flag
352
   Step-3: If the previous state of master is busy and bus-cycle
353
           is de-asserted, then reset the master and corresponding
354
           slave busy flag
355
 
356
*********************************************************/
357
 
358
always @(negedge rst_n or posedge clk) begin
359
   if(rst_n == 0) begin
360 10 dinesha
      master_busy   <= 0;
361
      slave_busy    <= 0;
362
   end else begin
363 2 dinesha
      for(i = 0; i < WB_MASTER; i = i + 1) begin
364
         if(master_busy[i] == 0) begin
365 10 dinesha
            if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
366
               slave_busy[wbd_taddr_master_t[i]]   <= 1;
367
               master_busy[i]              <= 1;
368 36 dinesha
            end
369
         end else if(wbd_cyc_master[i] == 0) begin
370
            master_busy[i]            <= 0;
371
            slave_busy[wbd_taddr_master_t[i]] <= 0;
372
         end
373
      end
374
   end
375
end
376
 
377
// Seperated non resetable two dimensional reg
378
always @(posedge clk) begin
379
      for(n = 0; n < WB_MASTER; n = n + 1) begin
380
         if(master_busy[n] == 0) begin
381
            if(wbd_stb_master[n] & slave_busy[wbd_taddr_master_t[n]] == 0) begin
382
               master_mx_id[n] <= wbd_taddr_master_t[n];
383
               slave_mx_id [wbd_taddr_master_t[n]] <= n;
384 2 dinesha
               // synopsys translate_off
385 36 dinesha
               // $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
386 2 dinesha
               // synopsys translate_on
387
            end
388 36 dinesha
         end else if(wbd_cyc_master[n] == 0) begin
389
            if(master_busy[n] == 1) begin
390 10 dinesha
            // synopsys translate_off
391 36 dinesha
            //  $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
392 10 dinesha
            // synopsys translate_on
393
            end
394 2 dinesha
         end
395
      end
396
end
397
 
398
 
399
endmodule

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