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[/] [oms8051mini/] [trunk/] [rtl/] [msg_handler/] [msg_handler.v] - Blame information for rev 28

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  UART Message Handler Module                                 ////
////                                                              ////
////  This file is part of the oms8051mini cores project          ////
////  http://www.opencores.org/cores/oms8051min/                  ////
////                                                              ////
////  Description                                                 ////
////  Uart Message Handler definitions.                           ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////  Revision:                                                   ////
////  v-0: 27 Nov 2016                                            ////
////       A. rtl file picked from                                ////
////           http://www.opencores.org/cores/uart2spi/           ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module msg_handler (
        reset_n ,
        sys_clk ,
 
 
    // UART-TX Information
        tx_data_avail,
        tx_rd,
        tx_data,
 
 
    // UART-RX Information
        rx_ready,
        rx_wr,
        rx_data,
 
      // Towards Register Interface
        reg_addr,
        reg_wr,
        reg_wdata,
        reg_req,
        reg_ack,
        reg_rdata
 
     );
 
 
// Define the Message Hanlde States
`define IDLE             4'h0
`define IDLE_TX_MSG1     4'h1
`define IDLE_TX_MSG2     4'h2
`define RX_CMD_PHASE     4'h3
`define WR_ADR_PHASE     4'h4
`define WR_DATA_PHASE    4'h5
`define SEND_WR_REQ      4'h6
`define RD_ADDR_PHASE    4'h7
`define SEND_RD_REQ      4'h8
`define SEND_RD_DATA     4'h9
`define TX_MSG           4'hA
 
`define BREAK_CHAR       8'h0A
 
//---------------------------------
// Global Dec
// ---------------------------------
 
input        reset_n               ; // line reset
input        sys_clk               ; // line clock
 
 
//--------------------------------------
// UART TXD Path
// -------------------------------------
output         tx_data_avail        ; // Indicate valid TXD Data available
output [7:0]   tx_data              ; // TXD Data to be transmited
input          tx_rd                ; // Indicate TXD Data Been Read
 
 
//--------------------------------------
// UART RXD Path
// -------------------------------------
output         rx_ready            ; // Indicate Ready to accept the Read Data
input [7:0]    rx_data             ; // RXD Data 
input          rx_wr               ; // Valid RXD Data
 
//---------------------------------------
// Control Unit interface
// --------------------------------------
 
output  [15:0] reg_addr           ; // Operend-1
output  [7:0]  reg_wdata          ; // Operend-2
output         reg_req            ; // Register Request
output         reg_wr             ; // 1 -> write; 0 -> read
input          reg_ack            ; // Register Ack
input   [7:0]  reg_rdata          ;
 
// Local Wire/Register Decleration
//
//
reg             tx_data_avail      ;
reg [7:0]       tx_data            ;
reg [16*8-1:0]  TxMsgBuf           ; // 16 Byte Tx Message Buffer
reg  [4:0]      TxMsgSize          ;
reg  [4:0]      RxMsgCnt           ; // Count the Receive Message Count
reg  [3:0]      State              ;
reg  [3:0]      NextState          ;
reg  [15:0]     cmd                ; // command
reg  [15:0]     reg_addr           ; // reg_addr
reg  [7:0]      reg_wdata          ; // reg_addr
reg             reg_wr             ; // 1 -> Reg Write request, 0 -> Read Requestion
reg             reg_req            ; // 1 -> Register request
 
 
wire rx_ready = 1;
/****************************************************************
*  UART Message Hanlding Steps
*
*  1. On Reset Or Unknown command, Send the Default Message
*     Select Option:
*     wr <addr> <data>
*     rd <addr>
*  2. Wait for User command <wr/rd>
*  3. On <wr> command move to write address phase;
*  phase
*       A. After write address phase move to write data phase
*       B. After write data phase, once user press \r command ; send register req
*          and write request and address + data
*       C. On receiving register ack response; send <success> message back and move
*          to state-2
*  3.  On <rd> command move to read address phase;
*       A. After read address phase , once user press '\r' command; send
*          register req , read request
*       C. On receiving register ack response; send <response + read_data> message and move
*          to state-2
*  *****************************************************************/
 
always @(negedge reset_n or posedge sys_clk)
begin
   if(reset_n == 1'b0) begin
      tx_data_avail <= 0;
      reg_req       <= 0;
      State         <= `IDLE;
      NextState     <= `IDLE;
   end else begin
   case(State)
      // Send Default Message
      `IDLE: begin
          TxMsgBuf      <= "Command Format:\n";  // Align to 16 character format by appending space character
          TxMsgSize     <= 16;
          tx_data_avail <= 0;
          State         <= `TX_MSG;
          NextState     <= `IDLE_TX_MSG1;
       end
 
      // Send Default Message (Contd..)
      `IDLE_TX_MSG1: begin
           TxMsgBuf      <= "wm <ad> <data>\n "; // Align to 16 character format by appending space character 
           TxMsgSize     <= 15;
           tx_data_avail <= 0;
           State         <= `TX_MSG;
           NextState     <= `IDLE_TX_MSG2;
        end
 
      // Send Default Message (Contd..)
      `IDLE_TX_MSG2: begin
           TxMsgBuf      <= "rm <ad>\n>>      ";  // Align to 16 character format by appending space character
           TxMsgSize     <= 10;
           tx_data_avail <= 0;
           RxMsgCnt      <= 0;
           State         <= `TX_MSG;
           NextState     <= `RX_CMD_PHASE;
      end
 
       // Wait for Response
    `RX_CMD_PHASE: begin
        if(rx_wr == 1) begin
           //if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the same
           if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the same
           //end else if(RxMsgCnt > 0 && rx_data == " ") begin // Check the command
           end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Check the command
             //if(cmd == "wm") begin
             if(cmd == 16'h776D) begin
                 RxMsgCnt <= 0;
                 reg_addr <= 0;
                 reg_wdata <= 0;
                 State <= `WR_ADR_PHASE;
              //end else if(cmd == "rm") begin
              end else if(cmd == 16'h726D) begin
                 reg_addr <= 0;
                 RxMsgCnt <= 0;
                 State <= `RD_ADDR_PHASE;
             end else begin // Unknow command
                State         <= `IDLE;
             end
           //end else if(rx_data == "\n") begin // Error State
           end else if(rx_data == `BREAK_CHAR) begin // Error State
              State         <= `IDLE;
           end
           else begin
              cmd <=  (cmd << 8) | rx_data ;
              RxMsgCnt <= RxMsgCnt+1;
           end
        end
     end
       // Write Address Phase 
    `WR_ADR_PHASE: begin
        if(rx_wr == 1) begin
           //if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the Space character
           if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the Space character
           //end else if(RxMsgCnt > 0 && rx_data == " ") begin // Move to write data phase
           end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Move to write data phase
              State         <= `WR_DATA_PHASE;
           //end else if(rx_data == "\n") begin // Error State
           end else if(rx_data == `BREAK_CHAR) begin // Error State
              State         <= `IDLE;
           end else begin
              reg_addr <= (reg_addr << 4) | char2hex(rx_data);
              RxMsgCnt <= RxMsgCnt+1;
           end
        end
     end
    // Write Data Phase 
    `WR_DATA_PHASE: begin
        if(rx_wr == 1) begin
           //if(rx_data == " ") begin // Ignore the Space character
           if(rx_data == 8'h20) begin // Ignore the Space character
           //end else if(rx_data == "\n") begin // Error State
           end else if(rx_data == `BREAK_CHAR) begin // Error State
              State           <= `SEND_WR_REQ;
              reg_wr          <= 1'b1; // Write request
              reg_req         <= 1'b1;
           end else begin // A to F
              reg_wdata <= (reg_wdata << 4) | char2hex(rx_data);
           end
        end
     end
    `SEND_WR_REQ: begin
        if(reg_ack)  begin
           reg_req       <= 1'b0;
           TxMsgBuf      <= "cmd success\n>>  "; // Align to 16 character format by appending space character 
           TxMsgSize     <= 14;
           tx_data_avail <= 0;
           State         <= `TX_MSG;
           NextState     <= `RX_CMD_PHASE;
       end
    end
 
       // Write Address Phase 
    `RD_ADDR_PHASE: begin
        if(rx_wr == 1) begin
           //if(rx_data == " ") begin // Ignore the Space character
           if(rx_data == 8'h20) begin // Ignore the Space character
           //end else if(rx_data == "\n") begin // Error State
           end else if(rx_data == `BREAK_CHAR) begin // Error State
              State           <= `SEND_RD_REQ;
              reg_wr          <= 1'b0; // Read request
              reg_req         <= 1'b1; // Reg Request
           end
           else begin // A to F
                 reg_addr     <= (reg_addr << 4) | char2hex(rx_data);
                 RxMsgCnt <= RxMsgCnt+1;
              end
           end
        end
 
    `SEND_RD_REQ: begin
        if(reg_ack)  begin
           reg_req       <= 1'b0;
           TxMsgBuf      <= "Response:       "; // Align to 16 character format by appending space character 
           TxMsgSize     <= 10;
           tx_data_avail <= 0;
           State         <= `TX_MSG;
           NextState     <= `SEND_RD_DATA;
       end
    end
    `SEND_RD_DATA: begin // Wait for Operation Completion
           TxMsgBuf[10*8-1:9*8]  <= hex2char(reg_rdata[7:4]);
           TxMsgBuf[9*8-1:8*8]   <= hex2char(reg_rdata[3:0]);
           TxMsgBuf[8*8-1:7*8]   <= "\n";
           TxMsgSize     <= 3;
           tx_data_avail <= 0;
           State         <= `TX_MSG;
           NextState     <= `RX_CMD_PHASE;
     end
 
       // Send Default Message (Contd..)
    `TX_MSG: begin
           tx_data_avail    <= 1;
           tx_data          <= TxMsgBuf[16*8-1:15*8];
           if(TxMsgSize == 0) begin
              tx_data_avail <= 0;
              State         <= NextState;
           end else if(tx_rd) begin
              TxMsgBuf      <= TxMsgBuf << 8;
              TxMsgSize     <= TxMsgSize -1;
           end
        end
   endcase
   end
end
 
 
// Character to hex number
function [3:0] char2hex;
input [7:0] data_in;
case (data_in)
     8'h30:     char2hex = 4'h0; // character '0' 
     8'h31:     char2hex = 4'h1; // character '1'
     8'h32:     char2hex = 4'h2; // character '2'
     8'h33:     char2hex = 4'h3; // character '3'
     8'h34:     char2hex = 4'h4; // character '4' 
     8'h35:     char2hex = 4'h5; // character '5'
     8'h36:     char2hex = 4'h6; // character '6'
     8'h37:     char2hex = 4'h7; // character '7'
     8'h38:     char2hex = 4'h8; // character '8'
     8'h39:     char2hex = 4'h9; // character '9'
     8'h41:     char2hex = 4'hA; // character 'A'
     8'h42:     char2hex = 4'hB; // character 'B'
     8'h43:     char2hex = 4'hC; // character 'C'
     8'h44:     char2hex = 4'hD; // character 'D'
     8'h45:     char2hex = 4'hE; // character 'E'
     8'h46:     char2hex = 4'hF; // character 'F'
     8'h61:     char2hex = 4'hA; // character 'a'
     8'h62:     char2hex = 4'hB; // character 'b'
     8'h63:     char2hex = 4'hC; // character 'c'
     8'h64:     char2hex = 4'hD; // character 'd'
     8'h65:     char2hex = 4'hE; // character 'e'
     8'h66:     char2hex = 4'hF; // character 'f'
      default :  char2hex = 4'hF;
   endcase
endfunction
 
// Hex to Asci Character 
function [7:0] hex2char;
input [3:0] data_in;
case (data_in)
     4'h0:      hex2char = 8'h30; // character '0' 
     4'h1:      hex2char = 8'h31; // character '1'
     4'h2:      hex2char = 8'h32; // character '2'
     4'h3:      hex2char = 8'h33; // character '3'
     4'h4:      hex2char = 8'h34; // character '4' 
     4'h5:      hex2char = 8'h35; // character '5'
     4'h6:      hex2char = 8'h36; // character '6'
     4'h7:      hex2char = 8'h37; // character '7'
     4'h8:      hex2char = 8'h38; // character '8'
     4'h9:      hex2char = 8'h39; // character '9'
     4'hA:      hex2char = 8'h41; // character 'A'
     4'hB:      hex2char = 8'h42; // character 'B'
     4'hC:      hex2char = 8'h43; // character 'C'
     4'hD:      hex2char = 8'h44; // character 'D'
     4'hE:      hex2char = 8'h45; // character 'E'
     4'hF:      hex2char = 8'h46; // character 'F'
   endcase
endfunction
endmodule

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Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [rtl/] [msg_handler/] [msg_handler.v] - Blame information for rev 28

Line No.	Rev	Author	Line
1	6	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// UART Message Handler Module ////`
4			`//// ////`
5			`//// This file is part of the oms8051mini cores project ////`
6			`//// http://www.opencores.org/cores/oms8051min/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Uart Message Handler definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17	19	dinesha	`//////////////////////////////////////////////////////////////////////`
18	6	dinesha	`//// Revision: ////`
19			`//// v-0: 27 Nov 2016 ////`
20			`//// A. rtl file picked from ////`
21			`//// http://www.opencores.org/cores/uart2spi/ ////`
22			`//////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`//////////////////////////////////////////////////////////////////////`
48
49	19	dinesha	`module msg_handler (`
50	6	dinesha	`reset_n ,`
51			`sys_clk ,`
52
53
54			`// UART-TX Information`
55			`tx_data_avail,`
56			`tx_rd,`
57			`tx_data,`
58
59
60			`// UART-RX Information`
61			`rx_ready,`
62			`rx_wr,`
63			`rx_data,`
64
65			`// Towards Register Interface`
66			`reg_addr,`
67			`reg_wr,`
68			`reg_wdata,`
69			`reg_req,`
70			`reg_ack,`
71			`reg_rdata`
72
73			`);`
74
75
76			`// Define the Message Hanlde States`
77			`define IDLE 4'h0
78			`define IDLE_TX_MSG1 4'h1
79			`define IDLE_TX_MSG2 4'h2
80			`define RX_CMD_PHASE 4'h3
81			`define WR_ADR_PHASE 4'h4
82			`define WR_DATA_PHASE 4'h5
83			`define SEND_WR_REQ 4'h6
84			`define RD_ADDR_PHASE 4'h7
85			`define SEND_RD_REQ 4'h8
86			`define SEND_RD_DATA 4'h9
87			`define TX_MSG 4'hA
88
89			`define BREAK_CHAR 8'h0A
90
91			`//---------------------------------`
92			`// Global Dec`
93			`// ---------------------------------`
94
95			`input reset_n ; // line reset`
96			`input sys_clk ; // line clock`
97
98
99			`//--------------------------------------`
100			`// UART TXD Path`
101			`// -------------------------------------`
102			`output tx_data_avail ; // Indicate valid TXD Data available`
103			`output [7:0] tx_data ; // TXD Data to be transmited`
104			`input tx_rd ; // Indicate TXD Data Been Read`
105
106
107			`//--------------------------------------`
108			`// UART RXD Path`
109			`// -------------------------------------`
110			`output rx_ready ; // Indicate Ready to accept the Read Data`
111			`input [7:0] rx_data ; // RXD Data`
112			`input rx_wr ; // Valid RXD Data`
113
114			`//---------------------------------------`
115			`// Control Unit interface`
116			`// --------------------------------------`
117
118			`output [15:0] reg_addr ; // Operend-1`
119	19	dinesha	`output [7:0] reg_wdata ; // Operend-2`
120	6	dinesha	`output reg_req ; // Register Request`
121			`output reg_wr ; // 1 -> write; 0 -> read`
122			`input reg_ack ; // Register Ack`
123	19	dinesha	`input [7:0] reg_rdata ;`
124	6	dinesha
125			`// Local Wire/Register Decleration`
126			`//`
127			`//`
128			`reg tx_data_avail ;`
129			`reg [7:0] tx_data ;`
130			`reg [16*8-1:0] TxMsgBuf ; // 16 Byte Tx Message Buffer`
131			`reg [4:0] TxMsgSize ;`
132			`reg [4:0] RxMsgCnt ; // Count the Receive Message Count`
133			`reg [3:0] State ;`
134			`reg [3:0] NextState ;`
135			`reg [15:0] cmd ; // command`
136			`reg [15:0] reg_addr ; // reg_addr`
137	19	dinesha	`reg [7:0] reg_wdata ; // reg_addr`
138	6	dinesha	`reg reg_wr ; // 1 -> Reg Write request, 0 -> Read Requestion`
139			`reg reg_req ; // 1 -> Register request`
140
141
142			`wire rx_ready = 1;`
143			`/****************************************************************`
144			`* UART Message Hanlding Steps`
145			`*`
146			`* 1. On Reset Or Unknown command, Send the Default Message`
147			`* Select Option:`
148			`* wr <addr> <data>`
149			`* rd <addr>`
150			`* 2. Wait for User command <wr/rd>`
151			`* 3. On <wr> command move to write address phase;`
152			`* phase`
153			`* A. After write address phase move to write data phase`
154			`* B. After write data phase, once user press \r command ; send register req`
155			`* and write request and address + data`
156			`* C. On receiving register ack response; send <success> message back and move`
157			`* to state-2`
158			`* 3. On <rd> command move to read address phase;`
159			`* A. After read address phase , once user press '\r' command; send`
160			`* register req , read request`
161			`* C. On receiving register ack response; send <response + read_data> message and move`
162			`* to state-2`
163			`* *****************************************************************/`
164
165			`always @(negedge reset_n or posedge sys_clk)`
166			`begin`
167			`if(reset_n == 1'b0) begin`
168			`tx_data_avail <= 0;`
169			`reg_req <= 0;`
170			State <= `IDLE;
171			NextState <= `IDLE;
172			`end else begin`
173			`case(State)`
174			`// Send Default Message`
175			`IDLE: begin
176			`TxMsgBuf <= "Command Format:\n"; // Align to 16 character format by appending space character`
177			`TxMsgSize <= 16;`
178			`tx_data_avail <= 0;`
179			State <= `TX_MSG;
180			NextState <= `IDLE_TX_MSG1;
181			`end`
182
183			`// Send Default Message (Contd..)`
184			`IDLE_TX_MSG1: begin
185			`TxMsgBuf <= "wm <ad> <data>\n "; // Align to 16 character format by appending space character`
186			`TxMsgSize <= 15;`
187			`tx_data_avail <= 0;`
188			State <= `TX_MSG;
189			NextState <= `IDLE_TX_MSG2;
190			`end`
191
192			`// Send Default Message (Contd..)`
193			`IDLE_TX_MSG2: begin
194			`TxMsgBuf <= "rm <ad>\n>> "; // Align to 16 character format by appending space character`
195			`TxMsgSize <= 10;`
196			`tx_data_avail <= 0;`
197			`RxMsgCnt <= 0;`
198			State <= `TX_MSG;
199			NextState <= `RX_CMD_PHASE;
200			`end`
201
202			`// Wait for Response`
203			`RX_CMD_PHASE: begin
204			`if(rx_wr == 1) begin`
205			`//if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the same`
206			`if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the same`
207			`//end else if(RxMsgCnt > 0 && rx_data == " ") begin // Check the command`
208			`end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Check the command`
209			`//if(cmd == "wm") begin`
210			`if(cmd == 16'h776D) begin`
211			`RxMsgCnt <= 0;`
212			`reg_addr <= 0;`
213			`reg_wdata <= 0;`
214			State <= `WR_ADR_PHASE;
215			`//end else if(cmd == "rm") begin`
216			`end else if(cmd == 16'h726D) begin`
217			`reg_addr <= 0;`
218			`RxMsgCnt <= 0;`
219			State <= `RD_ADDR_PHASE;
220			`end else begin // Unknow command`
221			State <= `IDLE;
222			`end`
223			`//end else if(rx_data == "\n") begin // Error State`
224			end else if(rx_data == `BREAK_CHAR) begin // Error State
225			State <= `IDLE;
226			`end`
227			`else begin`
228			`cmd <= (cmd << 8) \| rx_data ;`
229			`RxMsgCnt <= RxMsgCnt+1;`
230			`end`
231			`end`
232			`end`
233			`// Write Address Phase`
234			`WR_ADR_PHASE: begin
235			`if(rx_wr == 1) begin`
236			`//if(RxMsgCnt == 0 && rx_data == " ") begin // Ignore the Space character`
237			`if(RxMsgCnt == 0 && rx_data == 8'h20) begin // Ignore the Space character`
238			`//end else if(RxMsgCnt > 0 && rx_data == " ") begin // Move to write data phase`
239			`end else if(RxMsgCnt > 0 && rx_data == 8'h20) begin // Move to write data phase`
240			State <= `WR_DATA_PHASE;
241			`//end else if(rx_data == "\n") begin // Error State`
242			end else if(rx_data == `BREAK_CHAR) begin // Error State
243			State <= `IDLE;
244			`end else begin`
245			`reg_addr <= (reg_addr << 4) \| char2hex(rx_data);`
246			`RxMsgCnt <= RxMsgCnt+1;`
247			`end`
248			`end`
249			`end`
250			`// Write Data Phase`
251			`WR_DATA_PHASE: begin
252			`if(rx_wr == 1) begin`
253			`//if(rx_data == " ") begin // Ignore the Space character`
254			`if(rx_data == 8'h20) begin // Ignore the Space character`
255			`//end else if(rx_data == "\n") begin // Error State`
256			end else if(rx_data == `BREAK_CHAR) begin // Error State
257			State <= `SEND_WR_REQ;
258			`reg_wr <= 1'b1; // Write request`
259			`reg_req <= 1'b1;`
260			`end else begin // A to F`
261	19	dinesha	`reg_wdata <= (reg_wdata << 4) \| char2hex(rx_data);`
262	6	dinesha	`end`
263			`end`
264			`end`
265			`SEND_WR_REQ: begin
266			`if(reg_ack) begin`
267			`reg_req <= 1'b0;`
268			`TxMsgBuf <= "cmd success\n>> "; // Align to 16 character format by appending space character`
269			`TxMsgSize <= 14;`
270			`tx_data_avail <= 0;`
271			State <= `TX_MSG;
272			NextState <= `RX_CMD_PHASE;
273			`end`
274			`end`
275
276			`// Write Address Phase`
277			`RD_ADDR_PHASE: begin
278			`if(rx_wr == 1) begin`
279			`//if(rx_data == " ") begin // Ignore the Space character`
280			`if(rx_data == 8'h20) begin // Ignore the Space character`
281			`//end else if(rx_data == "\n") begin // Error State`
282			end else if(rx_data == `BREAK_CHAR) begin // Error State
283			State <= `SEND_RD_REQ;
284			`reg_wr <= 1'b0; // Read request`
285			`reg_req <= 1'b1; // Reg Request`
286			`end`
287			`else begin // A to F`
288			`reg_addr <= (reg_addr << 4) \| char2hex(rx_data);`
289			`RxMsgCnt <= RxMsgCnt+1;`
290			`end`
291			`end`
292			`end`
293
294			`SEND_RD_REQ: begin
295			`if(reg_ack) begin`
296			`reg_req <= 1'b0;`
297			`TxMsgBuf <= "Response: "; // Align to 16 character format by appending space character`
298			`TxMsgSize <= 10;`
299			`tx_data_avail <= 0;`
300			State <= `TX_MSG;
301			NextState <= `SEND_RD_DATA;
302			`end`
303			`end`
304			`SEND_RD_DATA: begin // Wait for Operation Completion
305			`TxMsgBuf[108-1:98] <= hex2char(reg_rdata[7:4]);`
306			`TxMsgBuf[98-1:88] <= hex2char(reg_rdata[3:0]);`
307			`TxMsgBuf[88-1:78] <= "\n";`
308	19	dinesha	`TxMsgSize <= 3;`
309	6	dinesha	`tx_data_avail <= 0;`
310			State <= `TX_MSG;
311			NextState <= `RX_CMD_PHASE;
312			`end`
313
314			`// Send Default Message (Contd..)`
315			`TX_MSG: begin
316			`tx_data_avail <= 1;`
317			`tx_data <= TxMsgBuf[168-1:158];`
318			`if(TxMsgSize == 0) begin`
319			`tx_data_avail <= 0;`
320			`State <= NextState;`
321			`end else if(tx_rd) begin`
322			`TxMsgBuf <= TxMsgBuf << 8;`
323			`TxMsgSize <= TxMsgSize -1;`
324			`end`
325			`end`
326			`endcase`
327			`end`
328			`end`
329
330
331			`// Character to hex number`
332			`function [3:0] char2hex;`
333			`input [7:0] data_in;`
334			`case (data_in)`
335			`8'h30: char2hex = 4'h0; // character '0'`
336			`8'h31: char2hex = 4'h1; // character '1'`
337			`8'h32: char2hex = 4'h2; // character '2'`
338			`8'h33: char2hex = 4'h3; // character '3'`
339			`8'h34: char2hex = 4'h4; // character '4'`
340			`8'h35: char2hex = 4'h5; // character '5'`
341			`8'h36: char2hex = 4'h6; // character '6'`
342			`8'h37: char2hex = 4'h7; // character '7'`
343			`8'h38: char2hex = 4'h8; // character '8'`
344			`8'h39: char2hex = 4'h9; // character '9'`
345			`8'h41: char2hex = 4'hA; // character 'A'`
346			`8'h42: char2hex = 4'hB; // character 'B'`
347			`8'h43: char2hex = 4'hC; // character 'C'`
348			`8'h44: char2hex = 4'hD; // character 'D'`
349			`8'h45: char2hex = 4'hE; // character 'E'`
350			`8'h46: char2hex = 4'hF; // character 'F'`
351			`8'h61: char2hex = 4'hA; // character 'a'`
352			`8'h62: char2hex = 4'hB; // character 'b'`
353			`8'h63: char2hex = 4'hC; // character 'c'`
354			`8'h64: char2hex = 4'hD; // character 'd'`
355			`8'h65: char2hex = 4'hE; // character 'e'`
356			`8'h66: char2hex = 4'hF; // character 'f'`
357			`default : char2hex = 4'hF;`
358			`endcase`
359			`endfunction`
360
361			`// Hex to Asci Character`
362			`function [7:0] hex2char;`
363			`input [3:0] data_in;`
364			`case (data_in)`
365			`4'h0: hex2char = 8'h30; // character '0'`
366			`4'h1: hex2char = 8'h31; // character '1'`
367			`4'h2: hex2char = 8'h32; // character '2'`
368			`4'h3: hex2char = 8'h33; // character '3'`
369			`4'h4: hex2char = 8'h34; // character '4'`
370			`4'h5: hex2char = 8'h35; // character '5'`
371			`4'h6: hex2char = 8'h36; // character '6'`
372			`4'h7: hex2char = 8'h37; // character '7'`
373			`4'h8: hex2char = 8'h38; // character '8'`
374			`4'h9: hex2char = 8'h39; // character '9'`
375			`4'hA: hex2char = 8'h41; // character 'A'`
376			`4'hB: hex2char = 8'h42; // character 'B'`
377			`4'hC: hex2char = 8'h43; // character 'C'`
378			`4'hD: hex2char = 8'h44; // character 'D'`
379			`4'hE: hex2char = 8'h45; // character 'E'`
380			`4'hF: hex2char = 8'h46; // character 'F'`
381			`endcase`
382			`endfunction`
383			`endmodule`