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[/] [oms8051mini/] [trunk/] [rtl/] [uart/] [uart_cfg.v] - Blame information for rev 37

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1 2 dinesha
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OMS 8051 cores UART Interface Module                        ////
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////                                                              ////
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////  This file is part of the OMS 8051 cores project             ////
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////  http://www.opencores.org/cores/oms8051mini/                 ////
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////                                                              ////
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////  Description                                                 ////
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////  OMS 8051 definitions.                                       ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
17 6 dinesha
////  Revision :                                                  //// 
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////     v-0.0 : Nov 26, 2016                                     ////
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////       1. Initial version picked from                         ////
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////       http://www.opencores.org/cores/turbo8051/              ////
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////     v-0.1 : Nov 28, 2016                                     ////
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////       1. Register access for Read/Write fifo & baudrate      ////
23 2 dinesha
////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
50
 
51
module uart_cfg (
52
 
53
             mclk,
54
             reset_n,
55
 
56
        // Reg Bus Interface Signal
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             reg_cs,
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             reg_wr,
59
             reg_addr,
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             reg_wdata,
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             reg_be,
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63
            // Outputs
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            reg_rdata,
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            reg_ack,
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67 6 dinesha
         // Uart Tx fifo interface
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            tx_fifo_full,
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            tx_fifo_wr_en,
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            tx_fifo_data,
71 2 dinesha
 
72 6 dinesha
         // Uart Rx fifo interface
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            rx_fifo_empty,
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            rx_fifo_rd_en,
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            rx_fifo_data,
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77 2 dinesha
       // configuration
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            cfg_tx_enable,
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            cfg_rx_enable,
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            cfg_stop_bit ,
81
            cfg_pri_mod  ,
82 6 dinesha
            cfg_baud_16x ,
83 2 dinesha
 
84
            frm_error_o,
85
            par_error_o,
86
            rx_fifo_full_err_o
87
 
88
        );
89
 
90
 
91
 
92 11 dinesha
input            mclk;
93
input            reset_n;
94 2 dinesha
 
95 6 dinesha
//--------------------------------
96
// Uart Tx fifo interface
97
//--------------------------------
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input            tx_fifo_full;
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output           tx_fifo_wr_en;
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output [7:0]     tx_fifo_data;
101
 
102
//--------------------------------
103
// Uart Rx fifo interface
104
//--------------------------------
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input            rx_fifo_empty;
106
output           rx_fifo_rd_en;
107
input [7:0]      rx_fifo_data;
108
 
109
//----------------------------------
110
// configuration
111
//----------------------------------
112 11 dinesha
output           cfg_tx_enable       ; // Tx Enable
113
output           cfg_rx_enable       ; // Rx Enable
114
output           cfg_stop_bit        ; // 0 -> 1 Stop, 1 -> 2 Stop
115
output [1:0]     cfg_pri_mod         ; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
116
output [11:0]    cfg_baud_16x        ; // 16x Baud clock config
117 2 dinesha
 
118 11 dinesha
input            frm_error_o         ; // framing error
119
input            par_error_o         ; // par error
120
input            rx_fifo_full_err_o  ; // rx fifo full error
121 2 dinesha
 
122
//---------------------------------
123
// Reg Bus Interface Signal
124
//---------------------------------
125
input             reg_cs         ;
126
input             reg_wr         ;
127
input [3:0]       reg_addr       ;
128 11 dinesha
input [7:0]       reg_wdata      ;
129
input             reg_be         ;
130 2 dinesha
 
131
// Outputs
132 11 dinesha
output [7:0]      reg_rdata      ;
133
output            reg_ack        ;
134 2 dinesha
 
135
 
136
 
137
//-----------------------------------------------------------------------
138
// Internal Wire Declarations
139
//-----------------------------------------------------------------------
140
 
141
wire           sw_rd_en;
142
wire           sw_wr_en;
143
wire  [3:0]    sw_addr ; // addressing 16 registers
144 11 dinesha
wire           wr_be   ;
145 2 dinesha
 
146 11 dinesha
reg   [7:0]  reg_rdata      ;
147 2 dinesha
reg           reg_ack     ;
148
 
149 11 dinesha
wire [7:0]    reg_0;  // Software_Reg_0
150
wire [7:0]    reg_1;  // Software-Reg_1
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wire [7:0]    reg_2;  // Software-Reg_2
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wire [7:0]    reg_3;  // Software-Reg_3
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wire [7:0]    reg_4;  // Software-Reg_4
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wire [7:0]    reg_5;  // Software-Reg_5
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wire [7:0]    reg_6;  // Software-Reg_6
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wire [7:0]    reg_7;  // Software-Reg_7
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wire [7:0]    reg_8;  // Software-Reg_8
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wire [7:0]    reg_9;  // Software-Reg_9
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wire [7:0]    reg_10; // Software-Reg_10
160
wire [7:0]    reg_11; // Software-Reg_11
161
wire [7:0]    reg_12; // Software-Reg_12
162
wire [7:0]    reg_13; // Software-Reg_13
163
wire [7:0]    reg_14; // Software-Reg_14
164
wire [7:0]    reg_15; // Software-Reg_15
165
reg  [7:0]    reg_out;
166 2 dinesha
 
167
//-----------------------------------------------------------------------
168
// Main code starts here
169
//-----------------------------------------------------------------------
170
 
171
//-----------------------------------------------------------------------
172
// Internal Logic Starts here
173
//-----------------------------------------------------------------------
174
    assign sw_addr       = reg_addr [3:0];
175
    assign sw_rd_en      = reg_cs & !reg_wr;
176
    assign sw_wr_en      = reg_cs & reg_wr;
177
    assign wr_be         = reg_be;
178
 
179
 
180
//-----------------------------------------------------------------------
181
// Read path mux
182
//-----------------------------------------------------------------------
183
 
184
always @ (posedge mclk or negedge reset_n)
185
begin : preg_out_Seq
186
   if (reset_n == 1'b0)
187
   begin
188 11 dinesha
      reg_rdata [7:0]  <= 8'h00;
189
      reg_ack          <= 1'b0;
190 2 dinesha
   end
191
   else if (sw_rd_en && !reg_ack)
192
   begin
193 11 dinesha
      reg_rdata [7:0]  <= reg_out [7:0];
194
      reg_ack          <= 1'b1;
195 2 dinesha
   end
196
   else if (sw_wr_en && !reg_ack)
197 11 dinesha
      reg_ack          <= 1'b1;
198 2 dinesha
   else
199
   begin
200
      reg_ack        <= 1'b0;
201
   end
202
end
203
 
204
 
205
//-----------------------------------------------------------------------
206
// register read enable and write enable decoding logic
207
//-----------------------------------------------------------------------
208
wire   sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
209
wire   sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
210
wire   sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
211
wire   sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
212
wire   sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
213
wire   sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
214
wire   sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
215
wire   sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
216
wire   sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
217
wire   sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
218
wire   sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
219
wire   sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
220
wire   sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
221
wire   sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
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wire   sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
223
wire   sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
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wire   sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
225
wire   sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
226
wire   sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
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wire   sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);
228
wire   sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
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wire   sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);
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wire   sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
231
wire   sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);
232
wire   sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC);
233
wire   sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC);
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wire   sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD);
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wire   sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD);
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wire   sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE);
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wire   sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE);
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wire   sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF);
239
wire   sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF);
240
 
241
 
242
always @( *)
243
begin : preg_sel_Com
244
 
245 11 dinesha
  reg_out [7:0] = 8'd0;
246 2 dinesha
 
247
  case (sw_addr [3:0])
248 11 dinesha
    4'b0000 : reg_out [7:0] = reg_0 [7:0];
249
    4'b0001 : reg_out [7:0] = reg_1 [7:0];
250
    4'b0010 : reg_out [7:0] = reg_2 [7:0];
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    4'b0011 : reg_out [7:0] = reg_3 [7:0];
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    4'b0100 : reg_out [7:0] = reg_4 [7:0];
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    4'b0101 : reg_out [7:0] = reg_5 [7:0];
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    4'b0110 : reg_out [7:0] = reg_6 [7:0];
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    4'b0111 : reg_out [7:0] = reg_7 [7:0];
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    4'b1000 : reg_out [7:0] = reg_8 [7:0];
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    4'b1001 : reg_out [7:0] = reg_9 [7:0];
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    4'b1010 : reg_out [7:0] = reg_10 [7:0];
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    4'b1011 : reg_out [7:0] = reg_11 [7:0];
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    4'b1100 : reg_out [7:0] = reg_12 [7:0];
261
    4'b1101 : reg_out [7:0] = reg_13 [7:0];
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    4'b1110 : reg_out [7:0] = reg_14 [7:0];
263
    4'b1111 : reg_out [7:0] = reg_15 [7:0];
264 2 dinesha
  endcase
265
end
266
 
267
 
268
 
269
//-----------------------------------------------------------------------
270
// Individual register assignments
271
//-----------------------------------------------------------------------
272
// Logic for Register 0 : uart Control Register
273
//-----------------------------------------------------------------------
274
wire [1:0]   cfg_pri_mod     = reg_0[4:3]; // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd
275
wire         cfg_stop_bit    = reg_0[2];   // 0 -> 1 Stop, 1 -> 2 Stop
276
wire         cfg_rx_enable   = reg_0[1];   // Rx Enable
277
wire         cfg_tx_enable   = reg_0[0];   // Tx Enable
278
 
279
generic_register #(5,0  ) u_uart_ctrl_be0 (
280
              .we            ({5{sw_wr_en_0 &
281 11 dinesha
                                 wr_be   }}  ),
282 2 dinesha
              .data_in       (reg_wdata[4:0]    ),
283
              .reset_n       (reset_n           ),
284
              .clk           (mclk              ),
285
 
286
              //List of Outs
287
              .data_out      (reg_0[4:0]        )
288
          );
289
 
290
 
291 11 dinesha
assign reg_0[7:5] = 3'h0;
292 2 dinesha
 
293
//-----------------------------------------------------------------------
294
// Logic for Register 1 : uart interrupt status
295
//-----------------------------------------------------------------------
296
stat_register u_intr_bit0 (
297
                 //inputs
298
                 . clk        (mclk            ),
299
                 . reset_n    (reset_n         ),
300
                 . cpu_we     (sw_wr_en_1 &
301 11 dinesha
                               wr_be        ),
302 2 dinesha
                 . cpu_ack    (reg_wdata[0]    ),
303
                 . hware_req  (frm_error_o     ),
304
 
305
                 //outputs
306
                 . data_out   (reg_1[0]        )
307
                 );
308
 
309
stat_register u_intr_bit1 (
310
                 //inputs
311
                 . clk        (mclk            ),
312
                 . reset_n    (reset_n         ),
313
                 . cpu_we     (sw_wr_en_1 &
314 11 dinesha
                               wr_be        ),
315 2 dinesha
                 . cpu_ack    (reg_wdata[1]    ),
316
                 . hware_req  (par_error_o     ),
317
 
318
                 //outputs
319
                 . data_out   (reg_1[1]        )
320
                 );
321
 
322
stat_register u_intr_bit2 (
323
                 //inputs
324
                 . clk        (mclk                ),
325
                 . reset_n    (reset_n             ),
326
                 . cpu_we     (sw_wr_en_1 &
327 11 dinesha
                               wr_be            ),
328 2 dinesha
                 . cpu_ack    (reg_wdata[2]        ),
329
                 . hware_req  (rx_fifo_full_err_o  ),
330
 
331
                 //outputs
332
                 . data_out   (reg_1[2]            )
333
                 );
334
 
335 11 dinesha
assign reg_1[7:3] = 5'h0;
336 2 dinesha
 
337
 
338 6 dinesha
//-----------------------------------------------------------------------
339
// Logic for Register 2 :  Baud Rate Control
340
//-----------------------------------------------------------------------
341 11 dinesha
wire [11:0]   cfg_baud_16x    = {reg_3[3:0],reg_2[7:0]};
342 2 dinesha
 
343 11 dinesha
generic_register #(8,0  ) u_uart_ctrl_reg2 (
344
              .we            ({8{sw_wr_en_2 &
345
                                 wr_be   }}  ),
346
              .data_in       (reg_wdata[7:0]    ),
347 6 dinesha
              .reset_n       (reset_n           ),
348
              .clk           (mclk              ),
349
 
350
              //List of Outs
351 11 dinesha
              .data_out      (reg_2[7:0]        )
352 6 dinesha
          );
353 2 dinesha
 
354 11 dinesha
generic_register #(4,0  ) u_uart_ctrl_reg3 (
355
              .we            ({4{sw_wr_en_3 &
356
                                 wr_be   }}  ),
357
              .data_in       (reg_wdata[3:0]    ),
358
              .reset_n       (reset_n           ),
359
              .clk           (mclk              ),
360
 
361
              //List of Outs
362
              .data_out      (reg_3[3:0]        )
363
          );
364 6 dinesha
 
365 11 dinesha
assign reg_3[7:4] = 4'h0;
366 6 dinesha
 
367
 
368 11 dinesha
// reg-4  status
369
//
370
assign reg_4[7:0] = {6'h0,rx_fifo_empty,tx_fifo_full};
371 6 dinesha
 
372 11 dinesha
// reg_5 is tx_fifo wr
373
assign tx_fifo_wr_en  = sw_wr_en_5 & reg_ack & !tx_fifo_full;
374 6 dinesha
assign tx_fifo_data   = reg_wdata[7:0];
375
 
376 11 dinesha
// reg_6 is rx_fifo read
377 6 dinesha
// rx_fifo read data
378 11 dinesha
assign reg_6[7:0] = {rx_fifo_data};
379
assign  rx_fifo_rd_en = sw_rd_en_6 & reg_ack & !rx_fifo_empty;
380 6 dinesha
 
381
 
382 2 dinesha
endmodule

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