Subversion Repositories oms8051mini

Reading J:/Microsemi/Libero_SoC_v11.7/Model/tcl/vsim/pref.tcl

# 10.4c

# vsim -do "run.do" -c tb_top "+uart_lb" "+INTERNAL_ROM"

# Start time: 11:09:03 on Jan 08,2017

# //  ModelSim Microsemi 10.4c Aug 12 2015

# //

# //  Copyright 1991-2015 Mentor Graphics Corporation

# //  All Rights Reserved.

# //

# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION

# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS

# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.

# //  THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL

# //  INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM

# //  DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552.

# //  FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER

# //  THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905.

# //

# Loading sv_std.std

# Loading work.tb_top

# ** Error: (vsim-7) Failed to open data file "F:/Yagna-Product/VLSI/opencores/oms8051mini/trunk/verif/run/work/delay/_primary.dat" in read mode.

#

# No such file or directory. (errno = ENOENT)

# Loading work.digital_core

# Loading work.clkgen

# Loading work.clk_ctl

# Loading work.msg_handler_top

# Loading work.uart_core_nf

# Loading work.uart_txfsm

# Loading work.uart_rxfsm

# Loading work.double_sync_low

# Loading work.msg_handler

# Loading work.wb_crossbar

# Loading work.uart_core

# Loading work.uart_cfg

# Loading work.generic_register

# Loading work.stat_register

# Loading work.async_fifo

# Loading work.spi_core

# Loading work.spi_if

# Loading work.spi_ctl

# Loading work.spi_cfg

# Loading work.req_register

# Loading work.i2cm_top

# Loading work.i2cm_byte_ctrl

# Loading work.i2cm_bit_ctrl

# Loading work.oc8051_top

# Loading work.oc8051_decoder

# Loading work.oc8051_alu

# Loading work.oc8051_multiply

# Loading work.oc8051_divide

# Loading work.oc8051_ram_top

# Loading work.oc8051_ram_256x8_two_bist

# Loading work.oc8051_alu_src_sel

# Loading work.oc8051_comp

# Loading work.oc8051_rom

# Loading work.oc8051_cy_select

# Loading work.oc8051_indi_addr

# Loading work.oc8051_memory_interface

# Loading work.oc8051_sfr

# Loading work.oc8051_acc

# Loading work.oc8051_b_register

# Loading work.oc8051_sp

# Loading work.oc8051_dptr

# Loading work.oc8051_psw

# Loading work.oc8051_ports

# Loading work.oc8051_int

# Loading work.oc8051_tc

# Loading work.oc8051_tc2

# Loading work.oc8051_xram

# Loading work.i2c_slave_model

# Loading work.uart_agent

# Loading work.m25p20

# Loading work.memory_access

# Loading work.acdc_check

# Loading work.internal_logic

# Loading work.AT45DB321

# Loading work.tb_glbl

# Loading work.bit_register

# ** Warning: (vsim-3017) ../tb/tb_top.v(135): [TFMPC] - Too few port connections. Expected 30, found 28.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core File: ../../rtl/core/digital_core.v

# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_mode'.

# ** Warning: (vsim-3722) ../tb/tb_top.v(135): [TFMPC] - Missing connection for port 'scan_enable'.

# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(233): [TFMPC] - Too few port connections. Expected 14, found 12.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/lib/async_fifo.v

# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'afull'.

# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(233): [TFMPC] - Missing connection for port 'aempty'.

# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(249): [TFMPC] - Too few port connections. Expected 14, found 12.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/lib/async_fifo.v

# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'afull'.

# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(249): [TFMPC] - Missing connection for port 'aempty'.

# ** Warning: (vsim-3017) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Too few port connections. Expected 56, found 53.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top/u_core/u_8051_core/u_memory_interface File: ../../rtl/8051/oc8051_memory_interface.v

# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'iack_i'.

# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'istb_o'.

# ** Warning: (vsim-3722) ../../rtl/8051/oc8051_top.v(522): [TFMPC] - Missing connection for port 'idat_i'.

# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(266): [TOFD] - System task or function '$shm_open' is not defined.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top File: ../tb/tb_top.v

# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(267): [TOFD] - System task or function '$shm_probe' is not defined.

#    Time: 0 ps  Iteration: 0  Instance: /tb_top File: ../tb/tb_top.v

# do run.do

# NOTE : Load memory with Initial delivery content

# NOTE : Initial Load End

# --> Dumpping the design

# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(266): Cannot execute undefined system task/function '$shm_open'

#

# ** Error (suppressible): (vsim-12023) ../tb/tb_top.v(267): Cannot execute undefined system task/function '$shm_probe'

#

# NOTE: COMMUNICATION (RE)STARTED

# DEBUG i2c_slave; stop condition detected at                  101

#

# ... Writing char 24 ...

# ... Write data 24 to UART done cnt :          1 ...

#

#

# ... Writing char 81 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  24

# ... Read Data from UART done cnt :         1...

# ... Write data 81 to UART done cnt :          2 ...

#

#

# ... Writing char 09 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  81

# ... Read Data from UART done cnt :         2...

# ... Write data 09 to UART done cnt :          3 ...

#

#

# ... Writing char 63 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  09

# ... Read Data from UART done cnt :         3...

# ... Write data 63 to UART done cnt :          4 ...

#

#

# ... Writing char 0d ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  63

# ... Read Data from UART done cnt :         4...

# ... Write data 0d to UART done cnt :          5 ...

#

#

# ... Writing char 8d ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0d

# ... Read Data from UART done cnt :         5...

# ... Write data 8d to UART done cnt :          6 ...

#

#

# ... Writing char 65 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  8d

# ... Read Data from UART done cnt :         6...

# ... Write data 65 to UART done cnt :          7 ...

#

#

# ... Writing char 12 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  65

# ... Read Data from UART done cnt :         7...

# ... Write data 12 to UART done cnt :          8 ...

#

#

# ... Writing char 01 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  12

# ... Read Data from UART done cnt :         8...

# ... Write data 01 to UART done cnt :          9 ...

#

#

# ... Writing char 0d ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  01

# ... Read Data from UART done cnt :         9...

# ... Write data 0d to UART done cnt :         10 ...

#

#

# ... Writing char 76 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0d

# ... Read Data from UART done cnt :        10...

# ... Write data 76 to UART done cnt :         11 ...

#

#

# ... Writing char 3d ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  76

# ... Read Data from UART done cnt :        11...

# ... Write data 3d to UART done cnt :         12 ...

#

#

# ... Writing char ed ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  3d

# ... Read Data from UART done cnt :        12...

# ... Write data ed to UART done cnt :         13 ...

#

#

# ... Writing char 8c ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  ed

# ... Read Data from UART done cnt :        13...

# ... Write data 8c to UART done cnt :         14 ...

#

#

# ... Writing char f9 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  8c

# ... Read Data from UART done cnt :        14...

# ... Write data f9 to UART done cnt :         15 ...

#

#

# ... Writing char c6 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  f9

# ... Read Data from UART done cnt :        15...

# ... Write data c6 to UART done cnt :         16 ...

#

#

# ... Writing char c5 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  c6

# ... Read Data from UART done cnt :        16...

# ... Write data c5 to UART done cnt :         17 ...

#

#

# ... Writing char aa ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  c5

# ... Read Data from UART done cnt :        17...

# ... Write data aa to UART done cnt :         18 ...

#

#

# ... Writing char e5 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  aa

# ... Read Data from UART done cnt :        18...

# ... Write data e5 to UART done cnt :         19 ...

#

#

# ... Writing char 77 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  e5

# ... Read Data from UART done cnt :        19...

# ... Write data 77 to UART done cnt :         20 ...

#

#

# ... Writing char 12 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  77

# ... Read Data from UART done cnt :        20...

# ... Write data 12 to UART done cnt :         21 ...

#

#

# ... Writing char 8f ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  12

# ... Read Data from UART done cnt :        21...

# ... Write data 8f to UART done cnt :         22 ...

#

#

# ... Writing char f2 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  8f

# ... Read Data from UART done cnt :        22...

# ... Write data f2 to UART done cnt :         23 ...

#

#

# ... Writing char ce ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  f2

# ... Read Data from UART done cnt :        23...

# ... Write data ce to UART done cnt :         24 ...

#

#

# ... Writing char e8 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  ce

# ... Read Data from UART done cnt :        24...

# ... Write data e8 to UART done cnt :         25 ...

#

#

# ... Writing char c5 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  e8

# ... Read Data from UART done cnt :        25...

# ... Write data c5 to UART done cnt :         26 ...

#

#

# ... Writing char 5c ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  c5

# ... Read Data from UART done cnt :        26...

# ... Write data 5c to UART done cnt :         27 ...

#

#

# ... Writing char bd ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  5c

# ... Read Data from UART done cnt :        27...

# ... Write data bd to UART done cnt :         28 ...

#

#

# ... Writing char 2d ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  bd

# ... Read Data from UART done cnt :        28...

# ... Write data 2d to UART done cnt :         29 ...

#

#

# ... Writing char 65 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  2d

# ... Read Data from UART done cnt :        29...

# ... Write data 65 to UART done cnt :         30 ...

#

#

# ... Writing char 63 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  65

# ... Read Data from UART done cnt :        30...

# ... Write data 63 to UART done cnt :         31 ...

#

#

# ... Writing char 0a ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  63

# ... Read Data from UART done cnt :        31...

# ... Write data 0a to UART done cnt :         32 ...

#

#

# ... Writing char 80 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0a

# ... Read Data from UART done cnt :        32...

# ... Write data 80 to UART done cnt :         33 ...

#

#

# ... Writing char 20 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  80

# ... Read Data from UART done cnt :        33...

# ... Write data 20 to UART done cnt :         34 ...

#

#

# ... Writing char aa ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  20

# ... Read Data from UART done cnt :        34...

# ... Write data aa to UART done cnt :         35 ...

#

#

# ... Writing char 9d ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  aa

# ... Read Data from UART done cnt :        35...

# ... Write data 9d to UART done cnt :         36 ...

#

#

# ... Writing char 96 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  9d

# ... Read Data from UART done cnt :        36...

# ... Write data 96 to UART done cnt :         37 ...

#

#

# ... Writing char 13 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  96

# ... Read Data from UART done cnt :        37...

# ... Write data 13 to UART done cnt :         38 ...

#

#

# ... Writing char 0d ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  13

# ... Read Data from UART done cnt :        38...

# ... Write data 0d to UART done cnt :         39 ...

#

#

# ... Writing char 53 ...

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  0d

# ... Read Data from UART done cnt :        39...

# ... Write data 53 to UART done cnt :         40 ...

#

# (tb_top.tb_uart.read_char_chk.loop_2) Data match  53

# ... Read Data from UART done cnt :        40...

# -------------------- Reporting Configuration --------------------

#       Data bit number setting is : 8

#       Stop bit number setting is : 1

#       Divisor of Uart clock   is : 15

#       Parity is disable

#       Even parity setting

#       FIFO mode is disable

# -----------------------------------------------------------------

# -------------------- Reporting Status --------------------

#

#       Number of character received is :    40

#       Number of character sent     is :    40

#       Number of parity error rxd   is :     0

#       Number of stop1  error rxd   is :     0

#       Number of stop2  error rxd   is :     0

#       Number of timeout error      is :     0

#       Number of error              is :     0

# -----------------------------------------------------------------

#

# -------------------------------------------------

# Test Status

# warnings: 0, errors: 0

#

# -------------------------------------------------

# Test Status

# warnings: 0, errors: 0

#

# =========

# Test Status: TEST PASSED

# =========

#

# ** Note: $finish    : ../lib/tb_glbl.v(70)

#    Time: 329091 ps  Iteration: 0  Instance: /tb_top

# End time: 11:09:07 on Jan 08,2017, Elapsed time: 0:00:04

# Errors: 3, Warnings: 15