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URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [verif/] [tb/] [tb_tasks.v] - Blame information for rev 12

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Line No. Rev Author Line
1 2 dinesha
 
2
initial
3
begin
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   reg_cs  = 0;
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   reg_be  = 4'h0;
6 10 dinesha
   reg_id  = 0;
7 2 dinesha
end
8
 
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task cpu_read;
10 10 dinesha
  input  [3:0]  block_id;
11 2 dinesha
  input  [15:0] address;
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  output [31:0] read_data;
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  begin
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      @(posedge app_clk);
15 10 dinesha
      reg_id  = block_id;
16 11 dinesha
 
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      // Byte-0
18 2 dinesha
      reg_cs = 1;
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      reg_wr = 0;
20 11 dinesha
      reg_be = 1'h1;
21 2 dinesha
      reg_addr = address;
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      @(posedge reg_ack);
23 11 dinesha
       #1 read_data[7:0] = reg_rdata[7:0];
24 2 dinesha
      @(posedge app_clk);
25 11 dinesha
       reg_cs  = 0;
26
 
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      // Byte-1
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      reg_cs = 1;
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      reg_wr = 0;
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      reg_be = 1'h1;
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      reg_addr = address+1;
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      @(posedge reg_ack);
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       #1 read_data[15:8]= reg_rdata[7:0];
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      @(posedge app_clk);
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       reg_cs  = 0;
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      // Byte-2
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      reg_cs = 1;
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      reg_wr = 0;
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      reg_be = 1'h1;
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      reg_addr = address+2;
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      @(posedge reg_ack);
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       #1 read_data[23:16]= reg_rdata[7:0];
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      @(posedge app_clk);
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       reg_cs  = 0;
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      // Byte-3
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      reg_cs = 1;
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      reg_wr = 0;
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      reg_be = 1'h1;
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      reg_addr = address+3;
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      @(posedge reg_ack);
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       #1 read_data[31:24] = reg_rdata[7:0];
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      @(posedge app_clk);
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       reg_cs  = 0;
56 2 dinesha
      //$display ("Config-Read: Id: %h Addr = %h, Data = %h", block_id,address, read_data);
57
  end
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endtask
59
 
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task cpu_write;
61 10 dinesha
  input  [3:0] block_id; // 0/1/2 --> ram/spi/uart 
62 2 dinesha
  input  [15:0] address;
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  input  [31:0] write_data;
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  begin
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      $display ("Config-Write: Id: %h Addr = %h, Cfg. Data = %h", block_id,address, write_data);
66 11 dinesha
      // Byte-0
67 2 dinesha
      @(posedge app_clk);
68 10 dinesha
      reg_id  = block_id;
69 2 dinesha
      reg_cs = 1;
70
      reg_wr = 1;
71 11 dinesha
      reg_be = 1'h1;
72 2 dinesha
      reg_addr = address;
73 11 dinesha
      reg_wdata = write_data[7:0];
74 2 dinesha
      @(posedge reg_ack);
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      @(posedge app_clk);
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      reg_cs  = 0;
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      reg_wr = 0;
78 11 dinesha
 
79
      // Byte-1
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      @(posedge app_clk);
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      reg_id  = block_id;
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      reg_cs = 1;
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      reg_wr = 1;
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      reg_be = 1'h1;
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      reg_addr = address+1;
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      reg_wdata = write_data[15:8];
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      @(posedge reg_ack);
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      @(posedge app_clk);
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      reg_cs  = 0;
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      reg_wr = 0;
91
 
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      // Byte-2
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      @(posedge app_clk);
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      reg_id  = block_id;
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      reg_cs = 1;
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      reg_wr = 1;
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      reg_be = 1'h1;
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      reg_addr = address+2;
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      reg_wdata = write_data[23:16];
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      @(posedge reg_ack);
101
      @(posedge app_clk);
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      reg_cs  = 0;
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      reg_wr = 0;
104
 
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      // Byte-2
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      @(posedge app_clk);
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      reg_id  = block_id;
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      reg_cs = 1;
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      reg_wr = 1;
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      reg_be = 1'h1;
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      reg_addr = address+3;
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      reg_wdata = write_data[31:24];
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      @(posedge reg_ack);
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      @(posedge app_clk);
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      reg_cs  = 0;
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      reg_wr = 0;
117
 
118 2 dinesha
  end
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endtask
120
 
121 11 dinesha
task cpu_byte_read;
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  input  [3:0]  block_id;
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  input  [15:0] address;
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  output [7:0] read_data;
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  begin
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      @(posedge app_clk);
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      reg_id  = block_id;
128
 
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      // Byte-0
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      reg_cs = 1;
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      reg_wr = 0;
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      reg_be = 1'h1;
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      reg_addr = address;
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      @(posedge reg_ack);
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       #1 read_data[7:0] = reg_rdata[7:0];
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      @(posedge app_clk);
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       reg_cs  = 0;
138
 
139
      //$display ("Config-Read: Id: %h Addr = %h, Data = %h", block_id,address, read_data);
140
  end
141
endtask
142
 
143
task cpu_byte_write;
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  input  [3:0] block_id; // 0/1/2 --> ram/spi/uart 
145
  input  [15:0] address;
146
  input  [7:0] write_data;
147
  begin
148
      $display ("Config-Write: Id: %h Addr = %h, Cfg. Data = %h", block_id,address, write_data);
149
      // Byte-0
150
      @(posedge app_clk);
151
      reg_id  = block_id;
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      reg_cs = 1;
153
      reg_wr = 1;
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      reg_be = 1'h1;
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      reg_addr = address;
156
      reg_wdata = write_data[7:0];
157
      @(posedge reg_ack);
158
      @(posedge app_clk);
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      reg_cs  = 0;
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      reg_wr = 0;
161
 
162
  end
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endtask
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