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skeptonomi |
----------------------------------------------------------------------------------
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-- <c>2018 william b hunter
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-- This file is part of ow2rtd.
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--
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-- ow2rtd is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lessor General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- ow2rtd is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU Lessor General Public License
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-- along with ow2rtd. If not, see <https://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------------------
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-- Create Date: 5/15/2018
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-- file: ds18b20_sim.vhd
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-- description: A simulation model for the DS18B20 temperature probe
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--
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-- Generics are used to set the device ID, the NVROM, and the timing model
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-- inputs are used to set the temperature to report back
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--
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-- This only simulates the SEARCH, ROM, SKIP, CONFIG, CONV, and READ commands
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-- save and recall to/from EEPROM were started, but not tested
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-- it is not a complete model. It does not validate timing.
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-----------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-------------------------------------------------------------------------------------
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-- Entity declaration
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-------------------------------------------------------------------------------------
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entity ds18b20_sim is
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generic (
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timing : in string := "ave";
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devid : in std_logic_vector(63 downto 0) := x"0000000000000128";
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nvrom : in std_logic_vector(23 downto 0) := x"3f0064"
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);
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port (
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--global signals
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pwrin : in std_logic; --tie to '1' if power provided, '0' if using parasitic power
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tempin : in real;
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dio : inout std_logic --synchronous reset
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);
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end ds18b20_sim;
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--library unisim;
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--use unisim.vcomponents.all;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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library work;
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architecture sim of ds18b20_sim is
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--low time to trigger a reaset
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constant tmin_rstl : time := 240 us;
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constant tave_rstl : time := 400 us;
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constant tmax_rstl : time := 480 us;
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signal trstl : time := tmin_rstl;
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--high time between reset pulse and presence pulse
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signal tpdih : time;
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constant tmin_pdih : time := 15 us;
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constant tave_pdih : time := 45 us;
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constant tmax_pdih : time := 60 us;
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--presence pulse low time
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signal tpdlo : time;
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constant tmin_pdlo : time := 60 us;
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constant tave_pdlo : time := 180 us;
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constant tmax_pdlo : time := 240 us;
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--write 0 low time
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signal tlow0 : time;
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constant tmin_low0 : time := 60 us;
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constant tave_low0 : time := 100 us;
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constant tmax_low0 : time := 120 us;
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--write 1 low time
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signal tlow1 : time;
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constant tmin_low1 : time := 1 us;
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constant tave_low1 : time := 10 us;
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constant tmax_low1 : time := 15 us;
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--master write data sample time
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signal tsamp : time := 1 us;
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constant tmin_samp : time := 15 us;
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constant tave_samp : time := 30 us;
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constant tmax_samp : time := 60 us;
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--slave read recovery time
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signal trec : time := 1 us;
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constant tmin_rec : time := 1 us;
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constant tave_rec : time := 3 us;
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constant tmax_rec : time := 6 us;
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--slave read data valid time
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signal trdv : time := 15 us;
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constant tmin_rdv : time := 15 us;
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constant tave_rdv : time := 30 us;
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constant tmax_rdv : time := 60 us;
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--recall from eeprom timing
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--note: dallas part does not spec this timing
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signal trecall : time := 100 us;
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--convert time
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signal tconv : time := 15 us;
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signal tconv9 : time := 15 us;
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constant tmax_conv9 : time := 93.75 us;
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constant tave_conv9 : time := tmax_conv9 * 2/3;
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constant tmin_conv9 : time := tmax_conv9 * 1/2;
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signal tconv10 : time := 15 us;
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constant tmax_conv10 : time := 93.75 us;
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constant tave_conv10 : time := tmax_conv10 * 2/3;
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constant tmin_conv10 : time := tmax_conv10 * 1/2;
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signal tconv11 : time := 15 us;
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constant tmax_conv11 : time := 93.75 us;
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constant tave_conv11 : time := tmax_conv11 * 2/3;
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constant tmin_conv11 : time := tmax_conv11 * 1/2;
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signal tconv12 : time := 15 us;
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constant tmax_conv12 : time := 93.75 us;
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constant tave_conv12 : time := tmax_conv12 * 2/3;
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constant tmin_conv12 : time := tmax_conv12 * 1/2;
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signal tcopy : time := 1 us;
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constant tmax_copy : time := 10 ms;
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constant tave_copy : time := 2 ms;
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constant tmin_copy : time := 1 ms;
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signal clk10m : std_logic;
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signal rstdet : std_logic := '0'; --indicates a detected a reset pulse from the master
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signal trise : time := now;
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signal tfall : time := now;
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signal rstdly : std_logic := '1';
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--signal tdif : time;
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signal timertime : time;
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signal timer : unsigned(15 downto 0);
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signal timertrig : std_logic := '0';
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signal timerdone : std_logic := '1';
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type state_type is (S_IDLE, S_RSTRESP,S_RSTRESP2,S_RSTRESP3,
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S_GETBYTE, S_GETBYTE2, S_PARSE,
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S_READROM, S_READROM2, S_SRCHROM, S_SRCHROMNOT, S_SRCHROMWR,
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S_MATCHROM, S_MATCHROM2, S_SRCHALARM, S_SKIPROM,
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S_PARSE2, S_CONV, S_COPY, S_WRITE1, S_WRITE2, S_WRITE3,
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S_READ, S_READRCVR, S_CRC, S_RECALL, S_RDPWR,
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S_START, S_MID, S_END);
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signal state : state_type := S_IDLE;
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signal nxt_state : state_type := S_IDLE;
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signal dout : std_logic := 'Z'; --read output bit from slave to master
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signal rstdout : std_logic := '1'; --read output bit from main process
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signal recalldout : std_logic := '1'; --read output bit from recall process
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signal copydout : std_logic := '1'; --read output bit from copy process
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signal convdout : std_logic := '1'; --read output bit from conv process
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signal readdout : std_logic := '1'; -- output data from read state machine
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signal din : std_logic := '1'; --resolved input data bit
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--signal rstout : std_logic := 'Z';
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signal bitcnt : integer;
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signal shiftbyte : std_logic_vector(7 downto 0);
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signal shiftid : std_logic_vector(63 downto 0);
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signal busy : std_logic := '0';
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--These signals are for the read state machine
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signal bitout : std_logic := '1'; --bit value to be read by master
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signal wrbitin : std_logic := '0'; -- the bit value written by the master
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signal wrbiterr : std_logic := '0'; -- indicates a master write pulse with an illegal timing
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signal writedet : std_logic := '0'; -- strobe indicating the master wrote a bit
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signal readen : std_logic := '0'; --enables the slave responses to the master read pulses
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signal readdet : std_logic := '0'; -- strobe indicating the master read a bit
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signal readdly : std_logic := '0'; -- delayed version of din for detecting read strobes
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signal readbit : std_logic := '0'; -- data to output from read state machine
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--signal readbit : std_logic := '0'; -- bit to drive the read output
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signal res : integer range 9 to 12; --high alram value in volatile mem
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signal alarmhi : std_logic := '0';
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signal alarmlo : std_logic := '0';
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signal trighi : std_logic_vector(7 downto 0) := nvrom(7 downto 0);
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signal triglo : std_logic_vector(7 downto 0) := nvrom(15 downto 8);
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--signal temp : std_logic_vector(15 downto 0); --last temperature conversion
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signal slvtemp : std_logic_vector(15 downto 0) := x"0190"; --the temperature read from device, default to 25C
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signal config : std_logic_vector(7 downto 0) := nvrom(23 downto 16);
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signal convtrig : std_logic := '0';
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signal convdone : std_logic := '1';
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signal copytrig : std_logic := '0';
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signal copydone : std_logic := '1';
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signal recalltrig : std_logic := '0';
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signal recalldone : std_logic := '1';
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signal eeprom : std_logic_vector(23 downto 0) := nvrom;
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signal scratch : std_logic_vector(63 downto 0) := x"1000ff" & nvrom & x"0000";
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signal crc : std_logic_vector(7 downto 0);
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begin
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trstl <= tmin_rstl when timing = "MIN" else tave_rstl when timing = "AVE" else tmax_rstl;
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tpdih <= tmin_pdih when timing = "MIN" else tave_pdih when timing = "AVE" else tmax_pdih;
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tpdlo <= tmin_pdlo when timing = "MIN" else tave_pdlo when timing = "AVE" else tmax_pdlo;
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tsamp <= tmin_samp when timing = "MIN" else tave_samp when timing = "AVE" else tmax_samp;
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trdv <= tmin_rdv when timing = "MIN" else tave_rdv when timing = "AVE" else tmax_rdv;
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tconv9 <= tmin_conv9 when timing = "MIN" else tave_conv9 when timing = "AVE" else tmax_conv9;
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tconv10 <= tmin_conv10 when timing = "MIN" else tave_conv10 when timing = "AVE" else tmax_conv10;
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tconv11 <= tmin_conv11 when timing = "MIN" else tave_conv11 when timing = "AVE" else tmax_conv11;
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tconv12 <= tmin_conv12 when timing = "MIN" else tave_conv12 when timing = "AVE" else tmax_conv12;
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tconv <= tconv9 when res = 9 else tconv10 when res=10 else tconv11 when res = 11 else tconv12;
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tcopy <= tmin_copy when timing = "MIN" else tave_copy when timing = "AVE" else tmax_copy;
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--rstdly <= dio after trstl;
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--rst <= '1' when rstdly = '0' and dio = '0' else '1';
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res <= 9 + to_integer(unsigned(config(6 downto 5)));
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p_clk10m : process
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begin
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clk10m <= '0';
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wait for 50 ns;
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clk10m <= '1';
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wait for 50 ns;
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end process;
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p_edges : process
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begin
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wait until din = '0';
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tfall <= now;
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wait until din = '1';
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trise <= now;
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end process;
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--this handles the master reseting this slave
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rstdly <= transport din after trstl;
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p_rst : process
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begin
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wait until rstdly = '0';
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--if last transition was falling edge and it was long ago...
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if tfall > trise and now - tfall >= trstl then
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rstdet <= '1';
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wait until din <= '1';
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rstdet <= '0';
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end if;
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end process;
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--p_readstb and p_read - work together to facilitate a read
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-- readen is set high to enable a read, then if din is low for 1 us the readdet signal triggers
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-- which causes readout to be driven low for a bit time if shift(0) is low
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-- after the bit time expires, din returns high, causing readdet to go low, and cycle is complete
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readdly <= transport din after 1us;
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p_readstb : process
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begin
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wait until readdly = '0';
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if tfall > trise and now - tfall >= 1us and readen = '1' then
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readdet <= '1';
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wait until din <= '1';
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readdet <= '0';
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end if;
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end process;
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p_read : process
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begin
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wait until readdet = '1' and readen = '1';
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readdout <= readbit;
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wait for trdv;
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readdout <= '1';
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end process;
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--this handles the master writing bits to this slave
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p_write : process
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begin
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wait until din = '1';
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--dont detect writes during read operations
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if readen = '0' and readdet = '0' then
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if now - tfall > tmin_low0 and now-tfall < tmax_low0 then
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wrbitin <= '0';
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writedet <= '1';
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wrbiterr <= '0';
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elsif now - tfall > tmin_low1 and now-tfall < tmax_low1 then
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wrbitin <= '1';
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writedet <= '1';
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wrbiterr <= '0';
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elsif now - tfall < trstl then
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wrbiterr <= '1';
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end if;
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end if;
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wait until din = '0';
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writedet <= '0';
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end process;
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p_timer : process(clk10m)
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begin
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if rising_edge(clk10m) then
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if timertrig = '1' then
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timer <= to_unsigned(integer(timertime/100 ns),16);
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timerdone <= '0';
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elsif timer > 1 then
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timer <= timer -1;
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else
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timerdone <= '1';
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end if;
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end if;
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end process;
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--this handles the master reading a bit from this slave
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--dout <= '0' when rdbiten = '1' and dout = '0' and now-tfall < trdv else '1';
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p_state :process(clk10m)
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begin
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if rising_edge (clk10m) then
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if rstdet = '1' then
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state <= S_RSTRESP;
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rstdout <= '1';
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readen <= '0';
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else
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case state is
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when S_IDLE =>
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rstdout <= '1';
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readen <= '0';
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bitcnt <= 0;
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convtrig <= '0';
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copytrig <= '0';
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recalltrig <= '0';
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shiftbyte <= x"00";
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shiftid <= devid;
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when S_RSTRESP =>
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readen <= '0';
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|
|
bitcnt <= 0;
|
323 |
|
|
rstdout <= '1';
|
324 |
|
|
shiftbyte <= x"00";
|
325 |
|
|
shiftid <= devid;
|
326 |
|
|
if timertrig = '0' and din = '1' then
|
327 |
|
|
timertime <= tpdih;
|
328 |
|
|
timertrig <= '1';
|
329 |
|
|
elsif timertrig = '1' then
|
330 |
|
|
timertrig <= '0';
|
331 |
|
|
state <= S_RSTRESP2;
|
332 |
|
|
end if;
|
333 |
|
|
when S_RSTRESP2 =>
|
334 |
|
|
if timertrig = '0' and timerdone = '1' then
|
335 |
|
|
rstdout <= '0';
|
336 |
|
|
timertime <= tpdlo;
|
337 |
|
|
timertrig <= '1';
|
338 |
|
|
elsif timertrig = '1' then
|
339 |
|
|
timertrig <= '0';
|
340 |
|
|
state <= S_RSTRESP3;
|
341 |
|
|
end if;
|
342 |
|
|
when S_RSTRESP3 =>
|
343 |
|
|
if timerdone = '1' then
|
344 |
|
|
rstdout <= '1';
|
345 |
|
|
state <= S_GETBYTE;
|
346 |
|
|
nxt_state <= S_PARSE;
|
347 |
|
|
end if;
|
348 |
|
|
when S_GETBYTE =>
|
349 |
|
|
if writedet = '0' then
|
350 |
|
|
state <= S_GETBYTE2;
|
351 |
|
|
end if;
|
352 |
|
|
when S_GETBYTE2 =>
|
353 |
|
|
if writedet = '1' then
|
354 |
|
|
shiftbyte <= wrbitin & shiftbyte(7 downto 1);
|
355 |
|
|
if bitcnt < 7 then
|
356 |
|
|
bitcnt <= bitcnt + 1;
|
357 |
|
|
state <= S_GETBYTE;
|
358 |
|
|
else
|
359 |
|
|
bitcnt <= 0;
|
360 |
|
|
state <= nxt_state;
|
361 |
|
|
end if;
|
362 |
|
|
end if;
|
363 |
|
|
when S_PARSE =>
|
364 |
|
|
shiftid <= devid;
|
365 |
|
|
case shiftbyte is
|
366 |
|
|
when x"33" => --read the rom id from the device, can only be used on single device bus
|
367 |
|
|
state <= S_READROM;
|
368 |
|
|
when x"55" => --match rom, used to address a single device on the bus
|
369 |
|
|
state <= S_MATCHROM;
|
370 |
|
|
when x"F0" => --use to find the devices on a multiple device bus
|
371 |
|
|
state <= S_SRCHROM;
|
372 |
|
|
when x"EC" => --search alarm, used to find devices that have active alarms
|
373 |
|
|
if alarmhi = '1' or alarmlo = '1' then
|
374 |
|
|
state <= S_SRCHROM;
|
375 |
|
|
else
|
376 |
|
|
state <= S_IDLE;
|
377 |
|
|
end if;
|
378 |
|
|
when x"CC" => --skip rom, skips rom addressing, for single device busses or broadcast commands
|
379 |
|
|
state <= S_GETBYTE;
|
380 |
|
|
nxt_state <= S_PARSE2;
|
381 |
|
|
when others =>
|
382 |
|
|
state <= S_IDLE;
|
383 |
|
|
end case;
|
384 |
|
|
when S_READROM =>
|
385 |
|
|
readen <= '1';
|
386 |
|
|
if readdet = '1' then
|
387 |
|
|
shiftid <= shiftid(0) & shiftid(63 downto 1);
|
388 |
|
|
if bitcnt < 55 then
|
389 |
|
|
bitcnt <= bitcnt + 1;
|
390 |
|
|
state <= S_READRCVR;
|
391 |
|
|
nxt_state <= S_READROM;
|
392 |
|
|
else
|
393 |
|
|
state <= S_CRC;
|
394 |
|
|
nxt_state <= S_READROM2;
|
395 |
|
|
shiftid <= x"00000000000000" & crc;
|
396 |
|
|
end if;
|
397 |
|
|
end if;
|
398 |
|
|
when S_READROM2 =>
|
399 |
|
|
state <= S_GETBYTE;
|
400 |
|
|
nxt_state <= S_PARSE2;
|
401 |
|
|
when S_MATCHROM =>
|
402 |
|
|
if writedet = '0' then
|
403 |
|
|
state <= S_MATCHROM2;
|
404 |
|
|
end if;
|
405 |
|
|
when S_MATCHROM2 =>
|
406 |
|
|
if writedet = '1' then
|
407 |
|
|
if wrbitin /= shiftid(0) then
|
408 |
|
|
state <= S_IDLE; --this part is removed from search, goto idle, wait for rstdet
|
409 |
|
|
else
|
410 |
|
|
shiftid <= shiftid(0) & shiftid(63 downto 1);
|
411 |
|
|
if bitcnt < 63 then
|
412 |
|
|
bitcnt <= bitcnt + 1;
|
413 |
|
|
state <= S_MATCHROM;
|
414 |
|
|
else
|
415 |
|
|
bitcnt <= 0;
|
416 |
|
|
state <= S_GETBYTE;
|
417 |
|
|
nxt_state <= S_PARSE2;
|
418 |
|
|
end if;
|
419 |
|
|
end if;
|
420 |
|
|
end if;
|
421 |
|
|
when S_SRCHROM =>
|
422 |
|
|
readen <= '1';
|
423 |
|
|
readbit <= shiftid(0);
|
424 |
|
|
if readdet = '1' then
|
425 |
|
|
state <= S_READRCVR;
|
426 |
|
|
nxt_state <= S_SRCHROMNOT;
|
427 |
|
|
end if;
|
428 |
|
|
when S_SRCHROMNOT =>
|
429 |
|
|
readen <= '1';
|
430 |
|
|
readbit <= not shiftid(0);
|
431 |
|
|
if readdet = '1' then
|
432 |
|
|
state <= S_READRCVR;
|
433 |
|
|
nxt_state <= S_SRCHROMWR;
|
434 |
|
|
end if;
|
435 |
|
|
when S_SRCHROMWR =>
|
436 |
|
|
readen <= '0';
|
437 |
|
|
if writedet = '1' then
|
438 |
|
|
if wrbitin /= shiftid(0) then
|
439 |
|
|
state <= S_IDLE; --this part is removed from search, goto idle, wait for rstdet
|
440 |
|
|
else
|
441 |
|
|
shiftid <= shiftid(0) & shiftid(63 downto 1);
|
442 |
|
|
if bitcnt < 63 then
|
443 |
|
|
bitcnt <= bitcnt + 1;
|
444 |
|
|
state <= S_SRCHROM;
|
445 |
|
|
else
|
446 |
|
|
bitcnt <= 0;
|
447 |
|
|
state <= S_GETBYTE;
|
448 |
|
|
nxt_state <= S_PARSE2;
|
449 |
|
|
end if;
|
450 |
|
|
end if;
|
451 |
|
|
end if;
|
452 |
|
|
when S_PARSE2 =>
|
453 |
|
|
case shiftbyte is
|
454 |
|
|
when x"44" => --convert temp
|
455 |
|
|
convtrig <= '1';
|
456 |
|
|
state <= S_CONV;
|
457 |
|
|
when x"48" => --copy scratchpad to eeprom
|
458 |
|
|
copytrig <= '1';
|
459 |
|
|
state <= S_COPY;
|
460 |
|
|
when x"4e" => --write scratchpad
|
461 |
|
|
state <= S_GETBYTE; -- data in order is Thi,Tlo,config
|
462 |
|
|
nxt_state <= S_WRITE1;
|
463 |
|
|
when x"be" => --read scratchpad
|
464 |
|
|
state <= S_READ; --data in order is TempLSB,TempMSB,AlarmHi,AlarmLo,config,FF,00,F0,CRC
|
465 |
|
|
shiftid <= x"1000ff" & config & trighi & triglo & slvtemp;
|
466 |
|
|
bitcnt <= 0;
|
467 |
|
|
when x"b8" => --recall scratchpad from eeprom
|
468 |
|
|
recalltrig <= '1';
|
469 |
|
|
state <= S_RECALL;
|
470 |
|
|
when x"b4" => --read the power bit to determine if parasitic;y powered
|
471 |
|
|
state <= S_RDPWR;
|
472 |
|
|
when others =>
|
473 |
|
|
state <= S_IDLE;
|
474 |
|
|
end case;
|
475 |
|
|
when S_CONV =>
|
476 |
|
|
if convtrig = '1' then
|
477 |
|
|
convtrig <= '0';
|
478 |
|
|
elsif convdone = '1' then
|
479 |
|
|
state <= S_IDLE;
|
480 |
|
|
end if;
|
481 |
|
|
when S_COPY =>
|
482 |
|
|
if copytrig = '1' then
|
483 |
|
|
copytrig <= '0';
|
484 |
|
|
elsif copydone = '1' then
|
485 |
|
|
state <= S_IDLE;
|
486 |
|
|
end if;
|
487 |
|
|
when S_WRITE1 =>
|
488 |
|
|
scratch(7 downto 0) <= shiftbyte;
|
489 |
|
|
state <= S_GETBYTE;
|
490 |
|
|
nxt_state <= S_WRITE2;
|
491 |
|
|
when S_WRITE2 =>
|
492 |
|
|
scratch(15 downto 8) <= shiftbyte;
|
493 |
|
|
state <= S_GETBYTE;
|
494 |
|
|
nxt_state <= S_WRITE3;
|
495 |
|
|
when S_WRITE3 =>
|
496 |
|
|
scratch(23 downto 16) <= '0' & shiftbyte(6 downto 5) & "11111";
|
497 |
|
|
state <= S_IDLE;
|
498 |
|
|
when S_RECALL =>
|
499 |
|
|
if recalltrig = '1' then
|
500 |
|
|
recalltrig <= '0';
|
501 |
|
|
elsif recalldone = '1' then
|
502 |
|
|
config <= eeprom(23 downto 16);
|
503 |
|
|
trighi <= eeprom(15 downto 8);
|
504 |
|
|
triglo <= eeprom(7 downto 0);
|
505 |
|
|
state <= S_IDLE;
|
506 |
|
|
end if;
|
507 |
|
|
when S_READ =>
|
508 |
|
|
readen <= '1';
|
509 |
|
|
readbit <= shiftid(0);
|
510 |
|
|
if readdet = '1' then
|
511 |
|
|
shiftid <= shiftid(0) & shiftid(63 downto 1);
|
512 |
|
|
if bitcnt < 63 then
|
513 |
|
|
bitcnt <= bitcnt + 1;
|
514 |
|
|
state <= S_READRCVR;
|
515 |
|
|
nxt_state <= S_READ;
|
516 |
|
|
else
|
517 |
|
|
state <= S_CRC;
|
518 |
|
|
nxt_state <= S_IDLE;
|
519 |
|
|
bitcnt <= 0;
|
520 |
|
|
shiftid <= x"00000000000000" & crc;
|
521 |
|
|
end if;
|
522 |
|
|
end if;
|
523 |
|
|
when S_READRCVR =>
|
524 |
|
|
readen <= '0';
|
525 |
|
|
if readdet = '0' then
|
526 |
|
|
state <= nxt_state;
|
527 |
|
|
end if;
|
528 |
|
|
when S_RDPWR =>
|
529 |
|
|
readen <= '1';
|
530 |
|
|
if readdet = '1' then
|
531 |
|
|
state <= S_READRCVR;
|
532 |
|
|
nxt_state <= S_IDLE;
|
533 |
|
|
end if;
|
534 |
|
|
when S_CRC =>
|
535 |
|
|
readen <= '1';
|
536 |
|
|
if readdet = '1' then
|
537 |
|
|
shiftid <= shiftid(0) & shiftid(63 downto 1);
|
538 |
|
|
if bitcnt < 7 then
|
539 |
|
|
bitcnt <= bitcnt + 1;
|
540 |
|
|
state <= S_READRCVR;
|
541 |
|
|
nxt_state <= S_READ;
|
542 |
|
|
else
|
543 |
|
|
state <= S_READRCVR;
|
544 |
|
|
nxt_state <= S_IDLE;
|
545 |
|
|
bitcnt <= 0;
|
546 |
|
|
shiftid <= x"00000000000000" & crc;
|
547 |
|
|
end if;
|
548 |
|
|
end if;
|
549 |
|
|
when others =>
|
550 |
|
|
state <= S_IDLE;
|
551 |
|
|
end case;
|
552 |
|
|
end if;
|
553 |
|
|
end if;
|
554 |
|
|
end process;
|
555 |
|
|
|
556 |
|
|
p_crc : process
|
557 |
|
|
begin
|
558 |
|
|
crc <= x"00";
|
559 |
|
|
wait until state = S_READ or state = S_READROM;
|
560 |
|
|
crc <= x"00";
|
561 |
|
|
while state = S_READ or state = S_READROM loop
|
562 |
|
|
wait until din = '0' or (state /= S_READ and state /= S_READROM);
|
563 |
|
|
if din = '0' then
|
564 |
|
|
if (crc(0) xor shiftid(0)) = '1' then
|
565 |
|
|
crc <= ('0' & crc(7 downto 1)) xor x"8c";
|
566 |
|
|
else
|
567 |
|
|
crc <= ('0' & crc(7 downto 1));
|
568 |
|
|
end if;
|
569 |
|
|
end if;
|
570 |
|
|
end loop;
|
571 |
|
|
end process;
|
572 |
|
|
|
573 |
|
|
|
574 |
|
|
p_convert : process
|
575 |
|
|
variable tstart : time := 0 us;
|
576 |
|
|
begin
|
577 |
|
|
convdout <= '1';
|
578 |
|
|
convdone <= '1';
|
579 |
|
|
wait until convtrig = '1';
|
580 |
|
|
convdone <= '0';
|
581 |
|
|
tstart := now;
|
582 |
|
|
while state = S_CONV loop
|
583 |
|
|
assert (din = '1' or pwrin = '1') report "power fail during parasitic powered conversion" severity error;
|
584 |
|
|
wait for 1 us;
|
585 |
|
|
if now - tstart > tconv then
|
586 |
|
|
convdone <= '1';
|
587 |
|
|
if res = 9 then
|
588 |
|
|
slvtemp <= std_logic_vector(to_signed(integer(tempin*2.0),13)) &"000";
|
589 |
|
|
elsif res = 10 then
|
590 |
|
|
slvtemp <= std_logic_vector(to_signed(integer(tempin*4.0),14)) &"00";
|
591 |
|
|
elsif res = 11 then
|
592 |
|
|
slvtemp <= std_logic_vector(to_signed(integer(tempin*8.0),15)) &'0';
|
593 |
|
|
else
|
594 |
|
|
slvtemp <= std_logic_vector(to_signed(integer(tempin*16.0),16));
|
595 |
|
|
end if;
|
596 |
|
|
if signed(slvtemp(11 downto 4)) < signed(trighi) then
|
597 |
|
|
alarmhi <= '0';
|
598 |
|
|
else
|
599 |
|
|
alarmhi <= '1';
|
600 |
|
|
end if;
|
601 |
|
|
if signed(slvtemp(11 downto 4)) > signed(triglo) then
|
602 |
|
|
alarmlo <= '0';
|
603 |
|
|
else
|
604 |
|
|
alarmlo <= '1';
|
605 |
|
|
end if;
|
606 |
|
|
elsif rstdet = '1' then
|
607 |
|
|
convdone <= '1';
|
608 |
|
|
elsif din = '0' and pwrin = '1' then
|
609 |
|
|
--master is reading convert ready bit
|
610 |
|
|
wait for 1 us;
|
611 |
|
|
convdout <= '0';
|
612 |
|
|
wait for trdv;
|
613 |
|
|
convdout <= '1';
|
614 |
|
|
end if;
|
615 |
|
|
end loop;
|
616 |
|
|
end process;
|
617 |
|
|
|
618 |
|
|
p_copy : process
|
619 |
|
|
variable tstart : time := 0 us;
|
620 |
|
|
begin
|
621 |
|
|
copydout <= '1';
|
622 |
|
|
wait until copytrig = '1';
|
623 |
|
|
copydone <= '0';
|
624 |
|
|
tstart := now;
|
625 |
|
|
wait for 10 us;
|
626 |
|
|
while state = S_COPY loop
|
627 |
|
|
assert (din = '1' or pwrin = '1') report "power fail during parasitic powered copy to eeprom" severity error;
|
628 |
|
|
wait for 1 us;
|
629 |
|
|
if now - tstart > tcopy then
|
630 |
|
|
copydone <= '1';
|
631 |
|
|
eeprom <= config & trighi & triglo;
|
632 |
|
|
elsif rstdet = '1' then
|
633 |
|
|
copydone <= '1';
|
634 |
|
|
elsif din = '0' then
|
635 |
|
|
--master is reading copy ready bit
|
636 |
|
|
wait for 1 us;
|
637 |
|
|
copydout <= '0';
|
638 |
|
|
wait for trdv;
|
639 |
|
|
copydout <= '1';
|
640 |
|
|
end if;
|
641 |
|
|
end loop;
|
642 |
|
|
end process;
|
643 |
|
|
|
644 |
|
|
|
645 |
|
|
|
646 |
|
|
p_recall : process
|
647 |
|
|
variable tstart : time := 0 us;
|
648 |
|
|
begin
|
649 |
|
|
recalldout <= '1';
|
650 |
|
|
wait until recalltrig = '1';
|
651 |
|
|
recalldone <= '0';
|
652 |
|
|
tstart := now;
|
653 |
|
|
wait for 10 us;
|
654 |
|
|
while state = S_RECALL loop
|
655 |
|
|
assert (din = '1' or pwrin = '1') report "power fail during parasitic recall from eeprom" severity error;
|
656 |
|
|
wait for 1 us;
|
657 |
|
|
if now - tstart > trecall then
|
658 |
|
|
recalldone <= '1';
|
659 |
|
|
elsif rstdet = '1' then
|
660 |
|
|
recalldone <= '1';
|
661 |
|
|
elsif din = '0' then
|
662 |
|
|
--master is reading recall ready bit
|
663 |
|
|
wait for 1 us;
|
664 |
|
|
recalldout <= '0';
|
665 |
|
|
wait for trdv;
|
666 |
|
|
recalldout <= '1';
|
667 |
|
|
end if;
|
668 |
|
|
end loop;
|
669 |
|
|
end process;
|
670 |
|
|
|
671 |
|
|
din <= '0' when dio = '0' else '1';
|
672 |
|
|
dout <= rstdout and copydout and convdout and recalldout and readdout;
|
673 |
|
|
dio <= '0' when dout = '0' else 'Z';
|
674 |
|
|
busy <= '0' when state = S_IDLE else '1';
|
675 |
|
|
|
676 |
|
|
end sim;
|