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skeptonomi |
----------------------------------------------------------------------------------
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-- <c>2018 william b hunter
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-- This file is part of ow2rtd.
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--
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-- ow2rtd is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lessor General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- ow2rtd is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU Lessor General Public License
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-- along with ow2rtd. If not, see <https://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------------------
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-- Create Date: 10/13/2023
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-- file: ds2405_sim.vhd
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-- description: A simulation model for the DS2405 addressable switch
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--
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-- Generics are used to set the device ID and the timing model
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--
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-- This only simulates the SEARCH, ROM, SKIP, CONFIG, CONV, and READ commands
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-----------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-------------------------------------------------------------------------------------
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-- Entity declaration
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-------------------------------------------------------------------------------------
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entity ds2405_sim is
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generic (
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timing : in string := "ave";
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devid : in std_logic_vector(63 downto 0) := x"1234567123456705"
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);
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port (
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--global signals
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pio : inout std_logic;
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dio : inout std_logic --synchronous reset
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);
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end ds2405_sim;
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--library unisim;
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--use unisim.vcomponents.all;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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library work;
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architecture sim of ds2405_sim is
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--low time to trigger a reaset
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constant tmin_rstl : time := 240 us;
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constant tave_rstl : time := 400 us;
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constant tmax_rstl : time := 480 us;
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signal trstl : time := tmin_rstl;
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--high time between reset pulse and presence pulse
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signal tpdih : time;
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constant tmin_pdih : time := 15 us;
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constant tave_pdih : time := 45 us;
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constant tmax_pdih : time := 60 us;
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--presence pulse low time
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signal tpdlo : time;
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constant tmin_pdlo : time := 60 us;
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constant tave_pdlo : time := 180 us;
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constant tmax_pdlo : time := 240 us;
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--write 0 low time
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signal tlow0 : time;
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constant tmin_low0 : time := 60 us;
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constant tave_low0 : time := 100 us;
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constant tmax_low0 : time := 120 us;
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--write 1 low time
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signal tlow1 : time;
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constant tmin_low1 : time := 1 us;
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constant tave_low1 : time := 10 us;
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constant tmax_low1 : time := 15 us;
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--master write data sample time
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signal tsamp : time := 1 us;
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constant tmin_samp : time := 15 us;
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constant tave_samp : time := 30 us;
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constant tmax_samp : time := 60 us;
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--slave read recovery time
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signal trec : time := 1 us;
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constant tmin_rec : time := 1 us;
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constant tave_rec : time := 3 us;
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constant tmax_rec : time := 6 us;
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--slave read data valid time
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signal trdv : time := 15 us;
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constant tmin_rdv : time := 15 us;
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constant tave_rdv : time := 30 us;
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constant tmax_rdv : time := 60 us;
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--recall from eeprom timing
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--note: dallas part does not spec this timing
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signal trecall : time := 100 us;
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signal tcopy : time := 1 us;
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constant tmax_copy : time := 10 ms;
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constant tave_copy : time := 2 ms;
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constant tmin_copy : time := 1 ms;
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signal clk10m : std_logic;
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signal rstdet : std_logic := '0'; --indicates a detected a reset pulse from the master
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signal trise : time := now;
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signal tfall : time := now;
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signal rstdly : std_logic := '1';
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--signal tdif : time;
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signal timertime : time;
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signal timer : unsigned(15 downto 0);
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signal timertrig : std_logic := '0';
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signal timerdone : std_logic := '1';
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signal switch : std_logic := '0';
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type state_type is (S_IDLE, S_RSTRESP,S_RSTRESP2,S_RSTRESP3,
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S_GETBYTE, S_GETBYTE2, S_PARSE,
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S_READROM, S_READROM2, S_SRCHROM, S_SRCHROMNOT, S_SRCHROMWR,
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S_MATCHROM, S_MATCHROM2, S_SRCHALARM, S_SKIPROM,
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S_PARSE2, S_READSW, S_WRITE1, S_WRITE2, S_WRITE3,
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S_READ, S_READRCVR, S_CRC);
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signal state : state_type := S_IDLE;
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signal nxt_state : state_type := S_IDLE;
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signal dout : std_logic := 'Z'; --read output bit from slave to master
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signal rstdout : std_logic := '1'; --read output bit from main process
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signal recalldout : std_logic := '1'; --read output bit from recall process
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signal copydout : std_logic := '1'; --read output bit from copy process
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signal convdout : std_logic := '1'; --read output bit from conv process
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signal readdout : std_logic := '1'; -- output data from read state machine
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signal din : std_logic := '1'; --resolved input data bit
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--signal rstout : std_logic := 'Z';
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signal bitcnt : integer;
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signal shiftbyte : std_logic_vector(7 downto 0);
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signal shiftid : std_logic_vector(63 downto 0);
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signal busy : std_logic := '0';
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--These signals are for the read state machine
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signal bitout : std_logic := '1'; --bit value to be read by master
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signal wrbitin : std_logic := '0'; -- the bit value written by the master
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signal wrbiterr : std_logic := '0'; -- indicates a master write pulse with an illegal timing
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signal writedet : std_logic := '0'; -- strobe indicating the master wrote a bit
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signal readen : std_logic := '0'; --enables the slave responses to the master read pulses
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signal readdet : std_logic := '0'; -- strobe indicating the master read a bit
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signal readdly : std_logic := '0'; -- delayed version of din for detecting read strobes
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signal readbit : std_logic := '0'; -- data to output from read state machine
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signal crc : std_logic_vector(7 downto 0);
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begin
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trstl <= tmin_rstl when timing = "MIN" else tave_rstl when timing = "AVE" else tmax_rstl;
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tpdih <= tmin_pdih when timing = "MIN" else tave_pdih when timing = "AVE" else tmax_pdih;
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tpdlo <= tmin_pdlo when timing = "MIN" else tave_pdlo when timing = "AVE" else tmax_pdlo;
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tsamp <= tmin_samp when timing = "MIN" else tave_samp when timing = "AVE" else tmax_samp;
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trdv <= tmin_rdv when timing = "MIN" else tave_rdv when timing = "AVE" else tmax_rdv;
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p_clk10m : process
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begin
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clk10m <= '0';
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wait for 50 ns;
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clk10m <= '1';
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wait for 50 ns;
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end process;
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p_edges : process
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begin
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wait until din = '0';
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tfall <= now;
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wait until din = '1';
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trise <= now;
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end process;
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--this handles the master reseting this slave
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rstdly <= transport din after trstl;
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p_rst : process
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begin
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wait until rstdly = '0';
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--if last transition was falling edge and it was long ago...
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if tfall > trise and now - tfall >= trstl then
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rstdet <= '1';
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wait until din <= '1';
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rstdet <= '0';
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end if;
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end process;
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--p_readstb and p_read - work together to facilitate a read
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-- readen is set high to enable a read, then if din is low for 1 us the readdet signal triggers
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-- which causes readout to be driven low for a bit time if shift(0) is low
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-- after the bit time expires, din returns high, causing readdet to go low, and cycle is complete
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readdly <= transport din after 1us;
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p_readstb : process
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begin
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wait until readdly = '0';
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if tfall > trise and now - tfall >= 1us and readen = '1' then
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readdet <= '1';
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wait until din <= '1';
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readdet <= '0';
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end if;
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end process;
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p_read : process
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begin
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wait until readdet = '1' and readen = '1';
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readdout <= readbit;
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wait for trdv;
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readdout <= '1';
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end process;
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--this handles the master writing bits to this slave
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p_write : process
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begin
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wait until din = '1';
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--dont detect writes during read operations
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if readen = '0' and readdet = '0' then
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if now - tfall > tmin_low0 and now-tfall < tmax_low0 then
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wrbitin <= '0';
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writedet <= '1';
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wrbiterr <= '0';
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elsif now - tfall > tmin_low1 and now-tfall < tmax_low1 then
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wrbitin <= '1';
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writedet <= '1';
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wrbiterr <= '0';
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elsif now - tfall < trstl then
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wrbiterr <= '1';
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end if;
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end if;
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wait until din = '0';
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writedet <= '0';
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end process;
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p_timer : process(clk10m)
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begin
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if rising_edge(clk10m) then
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if timertrig = '1' then
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timer <= to_unsigned(integer(timertime/100 ns),16);
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timerdone <= '0';
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elsif timer > 1 then
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timer <= timer -1;
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else
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timerdone <= '1';
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end if;
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end if;
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end process;
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--this handles the master reading a bit from this slave
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--dout <= '0' when rdbiten = '1' and dout = '0' and now-tfall < trdv else '1';
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p_state :process(clk10m)
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begin
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if rising_edge (clk10m) then
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if rstdet = '1' then
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state <= S_RSTRESP;
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rstdout <= '1';
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readen <= '0';
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else
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case state is
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when S_IDLE =>
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rstdout <= '1';
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readen <= '0';
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bitcnt <= 0;
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shiftbyte <= x"00";
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shiftid <= devid;
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when S_RSTRESP =>
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readen <= '0';
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bitcnt <= 0;
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rstdout <= '1';
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shiftbyte <= x"00";
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shiftid <= devid;
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if timertrig = '0' and din = '1' then
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timertime <= tpdih;
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timertrig <= '1';
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elsif timertrig = '1' then
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timertrig <= '0';
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state <= S_RSTRESP2;
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end if;
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when S_RSTRESP2 =>
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if timertrig = '0' and timerdone = '1' then
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rstdout <= '0';
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timertime <= tpdlo;
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timertrig <= '1';
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elsif timertrig = '1' then
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timertrig <= '0';
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state <= S_RSTRESP3;
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end if;
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when S_RSTRESP3 =>
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if timerdone = '1' then
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rstdout <= '1';
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state <= S_GETBYTE;
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nxt_state <= S_PARSE;
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end if;
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when S_GETBYTE =>
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if writedet = '0' then
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state <= S_GETBYTE2;
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end if;
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when S_GETBYTE2 =>
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if writedet = '1' then
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shiftbyte <= wrbitin & shiftbyte(7 downto 1);
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if bitcnt < 7 then
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bitcnt <= bitcnt + 1;
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state <= S_GETBYTE;
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else
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bitcnt <= 0;
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state <= nxt_state;
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end if;
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end if;
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310 |
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when S_PARSE =>
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shiftid <= devid;
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case shiftbyte is
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when x"33" => --read the rom id from the device, can only be used on single device bus
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state <= S_READROM;
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when x"55" => --match rom, used to address a single device on the bus
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state <= S_MATCHROM;
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when x"F0" => --use to find the devices on a multiple device bus
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state <= S_SRCHROM;
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when x"EC" => --search alarm, used to find devices that have the pio line pulled low
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if pio = '0' then
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state <= S_SRCHROM;
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else
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state <= S_IDLE;
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end if;
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325 |
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when x"CC" => --skip rom, skips rom addressing, for single device busses or broadcast commands
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326 |
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state <= S_GETBYTE;
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nxt_state <= S_PARSE2;
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when others =>
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state <= S_IDLE;
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end case;
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331 |
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when S_READROM =>
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332 |
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readen <= '1';
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333 |
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if readdet = '1' then
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334 |
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shiftid <= shiftid(0) & shiftid(63 downto 1);
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335 |
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if bitcnt < 55 then
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336 |
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bitcnt <= bitcnt + 1;
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337 |
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state <= S_READRCVR;
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338 |
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nxt_state <= S_READROM;
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339 |
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else
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340 |
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state <= S_CRC;
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341 |
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nxt_state <= S_READROM2;
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342 |
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shiftid <= x"00000000000000" & crc;
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343 |
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end if;
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344 |
|
|
end if;
|
345 |
|
|
when S_READROM2 =>
|
346 |
|
|
state <= S_GETBYTE;
|
347 |
|
|
nxt_state <= S_PARSE2;
|
348 |
|
|
when S_MATCHROM =>
|
349 |
|
|
if writedet = '0' then
|
350 |
|
|
state <= S_MATCHROM2;
|
351 |
|
|
end if;
|
352 |
|
|
when S_MATCHROM2 =>
|
353 |
|
|
if writedet = '1' then
|
354 |
|
|
if wrbitin /= shiftid(0) then
|
355 |
|
|
state <= S_IDLE; --this part is removed from search, goto idle, wait for rstdet
|
356 |
|
|
else
|
357 |
|
|
shiftid <= shiftid(0) & shiftid(63 downto 1);
|
358 |
|
|
if bitcnt < 63 then
|
359 |
|
|
bitcnt <= bitcnt + 1;
|
360 |
|
|
state <= S_MATCHROM;
|
361 |
|
|
else
|
362 |
|
|
bitcnt <= 0;
|
363 |
|
|
switch <= not switch;
|
364 |
|
|
state <= S_READSW;
|
365 |
|
|
end if;
|
366 |
|
|
end if;
|
367 |
|
|
end if;
|
368 |
|
|
when S_READSW =>
|
369 |
|
|
shiftid <= x"000000000000000" & "000" & pio;
|
370 |
|
|
readen <= '1';
|
371 |
|
|
if readdet = '1' then
|
372 |
|
|
state <= S_READRCVR;
|
373 |
|
|
nxt_state <= S_READSW;
|
374 |
|
|
end if;
|
375 |
|
|
when S_SRCHROM =>
|
376 |
|
|
readen <= '1';
|
377 |
|
|
readbit <= shiftid(0);
|
378 |
|
|
if readdet = '1' then
|
379 |
|
|
state <= S_READRCVR;
|
380 |
|
|
nxt_state <= S_SRCHROMNOT;
|
381 |
|
|
end if;
|
382 |
|
|
when S_SRCHROMNOT =>
|
383 |
|
|
readen <= '1';
|
384 |
|
|
readbit <= not shiftid(0);
|
385 |
|
|
if readdet = '1' then
|
386 |
|
|
state <= S_READRCVR;
|
387 |
|
|
nxt_state <= S_SRCHROMWR;
|
388 |
|
|
end if;
|
389 |
|
|
when S_SRCHROMWR =>
|
390 |
|
|
readen <= '0';
|
391 |
|
|
if writedet = '1' then
|
392 |
|
|
if wrbitin /= shiftid(0) then
|
393 |
|
|
state <= S_IDLE; --this part is removed from search, goto idle, wait for rstdet
|
394 |
|
|
else
|
395 |
|
|
shiftid <= shiftid(0) & shiftid(63 downto 1);
|
396 |
|
|
if bitcnt < 63 then
|
397 |
|
|
bitcnt <= bitcnt + 1;
|
398 |
|
|
state <= S_SRCHROM;
|
399 |
|
|
else
|
400 |
|
|
bitcnt <= 0;
|
401 |
|
|
state <= S_READSW;
|
402 |
|
|
end if;
|
403 |
|
|
end if;
|
404 |
|
|
end if;
|
405 |
|
|
when S_READRCVR =>
|
406 |
|
|
readen <= '0';
|
407 |
|
|
if readdet = '0' then
|
408 |
|
|
state <= nxt_state;
|
409 |
|
|
end if;
|
410 |
|
|
when S_CRC =>
|
411 |
|
|
readen <= '1';
|
412 |
|
|
if readdet = '1' then
|
413 |
|
|
shiftid <= shiftid(0) & shiftid(63 downto 1);
|
414 |
|
|
if bitcnt < 7 then
|
415 |
|
|
bitcnt <= bitcnt + 1;
|
416 |
|
|
state <= S_READRCVR;
|
417 |
|
|
nxt_state <= S_READ;
|
418 |
|
|
else
|
419 |
|
|
state <= S_READRCVR;
|
420 |
|
|
nxt_state <= S_IDLE;
|
421 |
|
|
bitcnt <= 0;
|
422 |
|
|
shiftid <= x"00000000000000" & crc;
|
423 |
|
|
end if;
|
424 |
|
|
end if;
|
425 |
|
|
when others =>
|
426 |
|
|
state <= S_IDLE;
|
427 |
|
|
end case;
|
428 |
|
|
end if;
|
429 |
|
|
end if;
|
430 |
|
|
end process;
|
431 |
|
|
|
432 |
|
|
p_crc : process
|
433 |
|
|
begin
|
434 |
|
|
crc <= x"00";
|
435 |
|
|
wait until state = S_READ or state = S_READROM;
|
436 |
|
|
crc <= x"00";
|
437 |
|
|
while state = S_READ or state = S_READROM loop
|
438 |
|
|
wait until din = '0' or (state /= S_READ and state /= S_READROM);
|
439 |
|
|
if din = '0' then
|
440 |
|
|
if (crc(0) xor shiftid(0)) = '1' then
|
441 |
|
|
crc <= ('0' & crc(7 downto 1)) xor x"8c";
|
442 |
|
|
else
|
443 |
|
|
crc <= ('0' & crc(7 downto 1));
|
444 |
|
|
end if;
|
445 |
|
|
end if;
|
446 |
|
|
end loop;
|
447 |
|
|
end process;
|
448 |
|
|
|
449 |
|
|
|
450 |
|
|
din <= '0' when dio = '0' else '1';
|
451 |
|
|
dout <= rstdout and copydout and convdout and recalldout and readdout;
|
452 |
|
|
dio <= '0' when dout = '0' else 'Z';
|
453 |
|
|
pio <= '0' when switch = '0' else 'H';
|
454 |
|
|
busy <= '0' when state = S_IDLE else '1';
|
455 |
|
|
|
456 |
|
|
end sim;
|