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skeptonomi |
----------------------------------------------------------------------------------
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-- <c>2018 william b hunter
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-- This file is part of ow2rtd.
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--
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-- ow2rtd is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lessor General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- ow2rtd is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU Lessor General Public License
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-- along with ow2rtd. If not, see <https://www.gnu.org/licenses/>.
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-----------------------------------------------------------------------------------
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-- Create Date: 5/15/2018
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-- file: ow_search.vhd
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-- description: searches a one wire bus for up to 8 one wire devices, and reports
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-- the 8 IDs. If there are more than 8 IDs or if a device disapears during the
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-- search it will activate the err flag. Only DS1820 devices are supported
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--
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-----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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-------------------------------------------------------------------------------------
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-- Entity declaration
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-------------------------------------------------------------------------------------
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entity ow_search is
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port (
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--global signals
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clk : in std_logic;
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srst : in std_logic;
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--signals to upper layer hierarchy
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start : in std_logic;
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busyin : in std_logic; --busy signal from either ow_byte or ow_bit
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busy : out std_logic; --busy indication to higher level modules
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error : out std_logic; --indicates a problem on the bus
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--signals to lower layer hierarchy (ow_bit and ow_byte)
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rdbit : out std_logic; --strobe to read a bit from ow_bit
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wrbit : out std_logic; --strobe to write a bit to ow_bit
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zzbit : out std_logic; --strobe to send/recieve init/response pulses
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obit : out std_logic; --the bit to write in a wrbit command to ow_bit
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ibit : in std_logic; --the data recieved from a rdbit command to the ow_bit
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wrbyte : out std_logic; --strobe to wrte a byte to ow_byte
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obyte : out std_logic_vector(7 downto 0); --data to write to the ow_byte
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--interface to id ram
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id_num : out std_logic_vector(4 downto 0); --index of the id to read or write
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id_bit : out std_logic_vector(5 downto 0); --index of the bit to read or write
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id_rbit : in std_logic; --bit value of the currently indexed bit of the current rom
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id_wbit : out std_logic; --bit value to write to the currently indexed bit
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id_we : out std_logic --write the currently indexed bit
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);
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end ow_search;
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-------------------------------------------------------------------------------------
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-- Architecture declaration
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-------------------------------------------------------------------------------------
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architecture rtl of ow_search is
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type h_state_type is (H_IDLE, H_RST, H_SKIP, H_READBIT, H_READCMP, H_PARSE, H_INCLOOP, H_FILL, H_ERROR);
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signal h_state : h_state_type := H_IDLE;
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type f_state_type is (F_IDLE, F_FIND, F_INC);
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signal f_state : f_state_type := F_IDLE;
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signal idcnt : integer range 0 to 31;
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signal lastfork : integer range 0 to 63;
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signal lastzero : integer range 0 to 63;
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signal idbitnum : integer range 0 to 63;
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signal lastdev : std_logic := '0';
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signal h_err : std_logic := '0';
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signal f_err : std_logic := '0';
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signal irdbit : std_logic := '0';
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signal iwrbit : std_logic := '0';
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signal iwe : std_logic := '0';
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signal iobit : std_logic := '0';
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signal iwrbyte : std_logic := '0';
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signal izzbit : std_logic := '0';
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signal rxpat : std_logic_vector(1 downto 0);
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signal h_start : std_logic := '0';
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signal restart : std_logic := '0';
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signal h_busy : std_logic := '0';
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constant scan_cmd : std_logic_vector(7 downto 0) := x"f0";
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attribute mark_debug : string;
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attribute mark_debug of f_state : signal is "true";
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attribute mark_debug of h_state : signal is "true";
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attribute mark_debug of idbitnum : signal is "true";
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attribute mark_debug of lastfork : signal is "true";
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attribute mark_debug of lastzero : signal is "true";
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attribute mark_debug of rxpat : signal is "true";
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attribute mark_debug of iwrbyte : signal is "true";
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attribute mark_debug of irdbit : signal is "true";
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attribute mark_debug of iwrbit : signal is "true";
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attribute mark_debug of iwe : signal is "true";
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attribute mark_debug of iobit : signal is "true";
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attribute mark_debug of id_rbit : signal is "true";
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attribute mark_debug of obyte : signal is "true";
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attribute mark_debug of lastdev : signal is "true";
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attribute mark_debug of start : signal is "true";
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attribute mark_debug of busyin : signal is "true";
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begin
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------------------------------------------------------
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-- HUNT - search for the next device on bus ---
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------------------------------------------------------
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--p_hunt - hunts for the next device using the algorithm described in Maxim (Analog Devices) app note APP187
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-- the app note is modified slightly for optimization in VHDL
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-- "restart" resets all parameters to rediscover all ROM iDs
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-- "hunt" searches for the next ROM ID in the sort order
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p_hunt : process (clk)
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begin
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if rising_edge(clk) then
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if srst = '1' or restart = '1' then
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h_state <= H_IDLE;
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idbitnum <= 0;
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lastfork <= 0;
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lastdev <= '0';
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rxpat <= "00";
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h_err <= '0';
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iwrbyte <= '0';
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izzbit <= '0';
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irdbit <= '0';
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iwrbit <= '0';
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iwe <= '0';
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iobit <= '0';
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obyte <= x"00";
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else
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case h_state is
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when H_IDLE =>
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idbitnum <= 0;
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lastzero <= 0;
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rxpat <= "00";
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iwrbyte <= '0';
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irdbit <= '0';
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iwrbit <= '0';
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iwe <= '0';
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iobit <= '0';
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obyte <= x"00";
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if h_start = '1' then
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if lastdev = '0' then
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h_state <= H_RST;
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izzbit <= '1';
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h_err <= '0';
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else
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h_state <= H_FILL;
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iwe <= '1';
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iobit <= '0';
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end if;
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else
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izzbit <= '0';
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end if;
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when H_RST =>
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if izzbit = '1' then
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izzbit <= '0';
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elsif busyin = '0' then
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if ibit = '1' then
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h_state <= H_ERROR;
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else
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obyte <= x"f0";
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iwrbyte <= '1';
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h_state <= H_SKIP;
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end if;
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end if;
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when H_SKIP =>
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if iwrbyte = '1' then
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iwrbyte <= '0';
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elsif busyin = '0' then
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irdbit <= '1';
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h_state <= H_READBIT;
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end if;
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when H_READBIT =>
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if irdbit = '1' then
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irdbit <= '0';
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elsif busyin = '0' then
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rxpat(1) <= ibit;
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irdbit <= '1';
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h_state <= H_READCMP;
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end if;
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when H_READCMP =>
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if irdbit = '1' then
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irdbit <= '0';
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elsif busyin = '0' then
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rxpat(0) <= ibit;
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h_state <= H_PARSE;
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end if;
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when H_PARSE =>
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case rxpat is
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when "11" =>
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h_state <= H_ERROR;
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when "00" =>
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if idbitnum = lastfork then
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--last_romid(63 downto 0) <= last_romid(0) & last_romid(63 downto 1);
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--new_romid(63 downto 0) <= '1' & new_romid(63 downto 1);
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iobit <= '1';
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iwrbit <= '1';
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iwe <= '1';
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h_state <= H_INCLOOP;
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elsif idbitnum > lastfork then
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--last_romid(63 downto 0) <= last_romid(0) & last_romid(63 downto 1);
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--new_romid(63 downto 0) <= '0' & new_romid(63 downto 1);
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iobit <= '0';
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iwrbit <= '1';
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iwe <= '1';
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lastzero <= idbitnum;
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h_state <= H_INCLOOP;
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else
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--last_romid(63 downto 0) <= last_romid(0) & last_romid(63 downto 1);
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--new_romid(63 downto 0) <= last_romid(0) & new_romid(63 downto 1);
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iobit <= id_rbit;
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iwrbit <= '1';
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iwe <= '1';
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if id_rbit = '0' then
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lastzero <= idbitnum;
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end if;
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h_state <= H_INCLOOP;
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end if;
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when others =>
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--last_romid(63 downto 0) <= last_romid(0) & last_romid(63 downto 1);
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--new_romid(63 downto 0) <= rxpat(1) & new_romid(63 downto 1);
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iobit <= rxpat(1);
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iwrbit <= '1';
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iwe <= '1';
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h_state <= H_INCLOOP;
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end case;
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when H_INCLOOP =>
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if iwrbit = '1' or iwe = '1' then
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iwrbit <= '0';
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iwe <= '0';
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elsif busyin = '0' then
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if idbitnum = 63 then
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h_state <= H_IDLE;
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lastfork <= lastzero;
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if lastzero = 0 then
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lastdev <= '1';
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end if;
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else
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idbitnum <= idbitnum + 1;
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irdbit <= '1';
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h_state <= H_READBIT;
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end if;
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end if;
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when H_FILL =>
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if iwe = '1' then
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iwe <= '0';
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elsif idbitnum = 63 then
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h_state <= H_IDLE;
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else
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idbitnum <= idbitnum + 1;
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iobit <= '0';
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iwe <= '1';
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end if;
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when others =>
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h_err <= '1';
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h_state <= H_IDLE;
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end case;
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end if;
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end if;
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end process p_hunt;
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h_busy <= '0' when h_state = H_IDLE and h_start = '0' else '1';
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------------------------------------------------------
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-- FINDALL - find all devices, one by one ---
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------------------------------------------------------
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--p_findall - finds all (at least up to 8) of the roms on the bus
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-- this process initiates up to 8 searches, each finds the next device
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-- in the sorted (by device ID) order.
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p_findall : process(clk)
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begin
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| 279 |
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if rising_edge(clk) then
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| 280 |
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if srst = '1' then
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idcnt <= 0;
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| 282 |
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f_state <= F_IDLE;
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restart <= '0';
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else
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case f_state is
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when F_IDLE =>
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| 287 |
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if start = '1' then
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restart <= '1';
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elsif restart = '1' then
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restart <= '0';
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h_start <= '1';
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f_state <= F_FIND;
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idcnt <= 0;
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f_err <= '0';
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end if;
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when F_FIND =>
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if h_start = '1' then
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h_start <= '0';
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| 299 |
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elsif h_busy = '0' then
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if h_err = '1' then
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f_state <= F_IDLE;
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f_err <= '1';
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else
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f_state <= F_INC;
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end if;
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end if;
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| 307 |
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when F_INC =>
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| 308 |
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if idcnt = 31 then
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idcnt <= 0;
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f_state <= F_IDLE;
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else
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idcnt <= idcnt + 1;
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f_state <= F_FIND;
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h_start <= '1';
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end if;
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| 316 |
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end case;
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| 317 |
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end if;
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| 318 |
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end if;
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| 319 |
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end process p_findall;
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| 320 |
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------------------------------------------------------
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| 322 |
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-- External Signals ---
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| 323 |
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------------------------------------------------------
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| 324 |
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| 325 |
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id_num <= std_logic_vector(to_unsigned(idcnt,5));
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| 326 |
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id_bit <= std_logic_vector(to_unsigned(idbitnum,6));
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| 327 |
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id_we <= iwe;
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| 328 |
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id_wbit <= iobit;
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| 329 |
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| 330 |
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rdbit <= irdbit;
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| 331 |
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wrbit <= iwrbit;
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| 332 |
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zzbit <= izzbit;
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| 333 |
|
|
obit <= iobit;
|
| 334 |
|
|
wrbyte <= iwrbyte;
|
| 335 |
|
|
|
| 336 |
|
|
busy <= '0' when f_state = F_IDLE and h_state = H_IDLE and start = '0' and restart = '0' else '1';
|
| 337 |
|
|
error <= f_err;
|
| 338 |
|
|
|
| 339 |
|
|
end rtl;
|
