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//////////////////////////////////////////////////////////////////
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// //
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// OoOPs Core Instruction Fetch Buffer module //
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// //
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// This file is part of the OoOPs project //
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// http://www.opencores.org/project,oops //
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// //
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// Description: //
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// Buffer for fetched instructions to help reduce penalty of //
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// cache misses during stall cycles. //
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// //
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// Author(s): //
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// - Joshua Smith, smjoshua@umich.edu //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2012 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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`include "ooops_defs.v"
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module if_buffer (
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input wire clk,
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input wire rst,
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input wire flush,
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// Write interface
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input wire if_valid,
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input wire [`INSTR_SZ-1:0] if_instr,
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input wire [`ADDR_SZ-1:0] if_fpc,
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input wire [`BP_SZ-1:0] if_bprd_info,
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// Read interface
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input wire if_ifb_pop_en,
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output wire ifb_full,
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output wire if_id_valid,
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output wire [`INSTR_SZ-1:0] if_id_instr,
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output wire [`ADDR_SZ-1:0] if_id_fpc,
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output wire [`BP_SZ-1:0] if_id_bprd_info
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);
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// Local wires
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wire [`IFB_PTR_SZ:0] ifb_rd_ptr, ifb_rd_ptr_in;
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wire [`IFB_PTR_SZ:0] ifb_wr_ptr, ifb_wr_ptr_in;
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wire [`IFB_ENTRIES-1:0] ifb_rd_ptr_vec; // 1-hot vector for reading
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wire ifb_empty;
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wire ifb_push;
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wire ifb_pop;
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wire [`IFB_PTR_SZ:0] ifb_valid_counter, ifb_valid_counter_in;
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wire ifb_valid_counter_ld;
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wire [`IFB_ENTRY_SZ-1:0] ifb_entry [`IFB_ENTRIES-1:0];
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wire [`IFB_ENTRY_SZ-1:0] ifb_entry_in;
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wire [`IFB_ENTRIES-1:0] ifb_entry_ld;
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reg [`IFB_ENTRY_SZ-1:0] ifb_rd_entry;
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// Handle muxing outputs
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integer i;
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always @* begin
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ifb_rd_entry = {`IFB_ENTRY_SZ{1'b0}};
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for (i=0; i<`IFB_ENTRIES; i=i+1) begin
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ifb_rd_entry = ifb_rd_entry | ({`IFB_ENTRY_SZ{ifb_rd_ptr_vec[i]}} & ifb_entry[i]);
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end
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end
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assign if_id_valid = !ifb_empty;
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assign {if_id_instr,if_id_fpc,if_id_bprd_info} = ifb_rd_entry;
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// Handle updating the read and write pointers
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assign ifb_push = if_valid & !ifb_full;
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assign ifb_pop = if_ifb_pop_en & !ifb_empty;
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assign ifb_wr_ptr_in = ((ifb_wr_ptr==`IFB_ENTRIES) | flush) ? {`IFB_PTR_SZ+1{1'b0}} : ifb_wr_ptr + 1;
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assign ifb_rd_ptr_in = ((ifb_rd_ptr==`IFB_ENTRIES) | flush) ? {`IFB_PTR_SZ+1{1'b0}} : ifb_rd_ptr + 1;
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wire [`IFB_ENTRIES-1:0] ifb_rd_ptr_vec_in = (`IFB_ENTRIES'h1 << ifb_rd_ptr_in);
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wire ifb_wr_ptr_ld = ifb_push | flush;
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wire ifb_rd_ptr_ld = ifb_pop | flush;
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MDFFLR #(`IFB_PTR_SZ+1) ifb_wr_ptr_ff (clk, rst, ifb_wr_ptr_ld, {`IFB_PTR_SZ+1{1'b0}}, ifb_wr_ptr_in, ifb_wr_ptr);
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MDFFLR #(`IFB_PTR_SZ+1) ifb_rd_ptr_ff (clk, rst, ifb_rd_ptr_ld, {`IFB_PTR_SZ+1{1'b0}}, ifb_rd_ptr_in, ifb_rd_ptr);
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MDFFLR #(`IFB_ENTRIES) ifb_rd_ptr_vec_ff (clk, rst, ifb_rd_ptr_ld, `IFB_ENTRIES'h1, ifb_rd_ptr_vec_in, ifb_rd_ptr_vec);
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// Handle occupancy detection
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wire ifb_full_in = (ifb_wr_ptr_in[`IFB_PTR_SZ] ^ ifb_rd_ptr_in[`IFB_PTR_SZ]) & (ifb_wr_ptr_in[`IFB_PTR_SZ-1:0]==ifb_rd_ptr_in[`IFB_PTR_SZ-1:0]);
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wire ifb_empty_in = (ifb_wr_ptr_in[`IFB_PTR_SZ] ~^ ifb_rd_ptr_in[`IFB_PTR_SZ]) & (ifb_wr_ptr_in[`IFB_PTR_SZ-1:0]==ifb_rd_ptr_in[`IFB_PTR_SZ-1:0]);
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MDFFR #(1) ifb_full_ff (clk, rst, 1'b0, ifb_full_in, ifb_full);
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MDFFR #(1) ifb_empty_ff (clk, rst, 1'b1, ifb_empty_in, ifb_empty);
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// Instantiate flops for entries
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assign ifb_entry_in = {if_valid,if_instr, if_fpc, if_bprd_info};
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genvar g;
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generate
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for (g=0; g<`IFB_ENTRIES; g=g+1)
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begin : ifb_entry_gen
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MDFFL #(`IFB_ENTRY_SZ) entry_ff (clk, ifb_entry_ld[g], ifb_entry_in, ifb_entry[g]);
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end
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endgenerate
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endmodule
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