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//////////////////////////////////////////////////////////////////
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// //
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// OoOPs Core Register Map Table module //
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// //
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// This file is part of the OoOPs project //
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// http://www.opencores.org/project,oops //
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// //
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// Description: //
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// The Map Table is responsible for maintaining the mapping //
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// from architectural->physical registers. This block //
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// consists of a free list for allocating new physical //
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// registers and also the tables for mapping source operands. //
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// //
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// To avoid excessive flop usage for the map tables, block rams//
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// will be used instead. //
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// //
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// Author(s): //
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// - Joshua Smith, smjoshua@umich.edu //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2012 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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`include "ooops_defs.v"
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module map_table (
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input wire clk,
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input wire rst,
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output wire map_table_init,
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// Rename port
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input wire ds1_valid,
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input wire [`REG_IDX_SZ-1:0] ds1_src1_idx,
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input wire [`REG_IDX_SZ-1:0] ds1_src2_idx,
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input wire [`REG_IDX_SZ-1:0] ds1_dest_idx,
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input wire ds1_dest_wr,
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input wire ds1_type_br,
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output wire [`TAG_SZ-1:0] ds2_src1_tag,
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output wire [`TAG_SZ-1:0] ds2_src2_tag,
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output wire ds2_src1_valid,
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output wire ds2_src2_valid,
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output wire [`TAG_SZ-1:0] ds2_dest_tag,
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output wire [`TAG_SZ-1:0] ds2_dest_tag_old,
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output wire [`FL_PTR_SZ-1:0] ds2_fl_head_ptr,
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output wire [`CHKPT_PTR_SZ-1:0] ds2_chkpt_ptr,
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// Writeback port
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//input wire [`CDB_BUS_SZ-1:0] ex_cdb_bus,
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// Retire and flush port
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input wire rob_pipe_flush,
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input wire rob_ds_ret_valid,
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input wire rob_ds_ret_dest_write,
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input wire [`CHKPT_PTR_SZ-1:0] rob_ds_chkpt_ptr,
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input wire [`FL_PTR_SZ-1:0] rob_ds_fl_head_ptr,
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input wire rob_ds_ret_chkpt_free,
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input wire [`REG_IDX_SZ-1:0] rob_ds_ret_idx,
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input wire [`TAG_SZ-1:0] rob_ds_ret_tag,
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input wire [`TAG_SZ-1:0] rob_ds_ret_tag_old
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);
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// Internal wires and regs
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wire [`TAG_SZ-1:0] ds1_dest_tag;
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wire [`FL_PTR_SZ-1:0] ds1_fl_head_ptr;
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wire [`ARCH_REGS-1:0] dfa_dirty_bit [`CHKPT_NUM-1:0];
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wire [`ARCH_REGS-1:0] dfa_dirty_bit_in [`CHKPT_NUM-1:0];
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wire [`CHKPT_NUM-1:0] dfa_dirty_bit_ld; // load is per checkpoint/column
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wire [`CHKPT_NUM-1:0] dfa_dirty_bit_row [`ARCH_REGS-1:0];
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wire [`CHKPT_PTR_SZ-1:0] ds1_src1_chkpt, ds1_src2_chkpt, ds1_dest_chkpt;
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wire [`CHKPT_PTR_SZ-1:0] chkpt_head_ptr;
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wire [`CHKPT_PTR_SZ-1:0] chkpt_head_ptr_p1;
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wire [`CHKPT_PTR_SZ-1:0] chkpt_tail_ptr;
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wire [`CHKPT_PTR_SZ-1:0] chkpt_tail_ptr_p1;
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wire [`CHKPT_NUM-1:0] chkpt_valid_mask;
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wire [`CHKPT_NUM-1:0] chkpt_valid_mask_in;
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wire chkpt_allocate;
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genvar g,k;
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// Instantiate free list
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free_list fl (
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.clk(clk),
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.rst(rst),
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.ds1_dest_wr(ds1_dest_wr),
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.rob_pipe_flush(rob_pipe_flush),
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.rob_ds_fl_head_ptr(rob_ds_fl_head_ptr),
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.rob_ds_ret_valid(rob_ds_ret_valid),
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.rob_ds_ret_dest_write(rob_ds_ret_dest_write),
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.rob_ds_ret_tag_old(rob_ds_ret_tag_old),
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.ds1_dest_tag(ds1_dest_tag),
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.ds1_fl_head_ptr(ds1_fl_head_ptr)
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);
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// Maintain the checkpoint head/tail pointers
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// Operation:
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// - Upon a pipe flush, restore both head and tail pointers to same pointer value from the ROB.
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// - When a new checkpoint is allocated, advance head pointer by 1
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// - When an instruction which allocated a checkpoint retires, advance tail pointer by 1.
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assign chkpt_allocate = ds1_type_br & ~rob_pipe_flush;
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wire [`CHKPT_PTR_SZ-1:0] chkpt_head_ptr_in = rob_pipe_flush ? rob_ds_chkpt_ptr : chkpt_head_ptr_p1;
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wire [`CHKPT_PTR_SZ-1:0] chkpt_tail_ptr_in = rob_pipe_flush ? rob_ds_chkpt_ptr : chkpt_tail_ptr_p1;
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wire chkpt_head_ptr_ld = rob_pipe_flush | chkpt_allocate;
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wire chkpt_tail_ptr_ld = rob_pipe_flush | (rob_ds_ret_valid & rob_ds_ret_chkpt_free);
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MDFFLR #(`CHKPT_PTR_SZ) chkpt_head_ptr_ff (clk, rst, chkpt_head_ptr_ld, `CHKPT_PTR_SZ'h0, chkpt_head_ptr_in, chkpt_head_ptr);
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MDFFLR #(`CHKPT_PTR_SZ) chkpt_tail_ptr_ff (clk, rst, chkpt_tail_ptr_ld, `CHKPT_PTR_SZ'h0, chkpt_tail_ptr_in, chkpt_tail_ptr);
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assign chkpt_head_ptr_p1 = (chkpt_head_ptr == `CHKPT_NUM-1) ? `CHKPT_PTR_SZ'h0 : chkpt_head_ptr + `CHKPT_PTR_SZ'h1;
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assign chkpt_tail_ptr_p1 = (chkpt_tail_ptr == `CHKPT_NUM-1) ? `CHKPT_PTR_SZ'h0 : chkpt_tail_ptr + `CHKPT_PTR_SZ'h1;
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// Keep a bit-vector mask of valid (allocated) checkpoints for the DFA search
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// Initialize checkpoint 0 to valid, this will be the checkpoint used out of reset.
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wire [`CHKPT_NUM-1:0] allocated_chkpt = (`CHKPT_NUM'h1 << chkpt_head_ptr_p1) & {`CHKPT_NUM{chkpt_allocate}};
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wire [`CHKPT_NUM-1:0] freed_chkpt = (`CHKPT_NUM'h1 << chkpt_tail_ptr) & {`CHKPT_NUM{rob_ds_ret_chkpt_free}};
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wire [`CHKPT_NUM-1:0] rob_ds_chkpt_vec = (`CHKPT_NUM'h1 << rob_ds_chkpt_ptr);
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assign chkpt_valid_mask_in = rob_pipe_flush ? rob_ds_chkpt_vec : ((chkpt_valid_mask | allocated_chkpt) & ~freed_chkpt);
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MDFFLR #(`CHKPT_NUM) chkpt_valid_mask_ff (clk, rst, chkpt_head_ptr_ld | chkpt_tail_ptr_ld, `CHKPT_NUM'h1, chkpt_valid_mask_in, chkpt_valid_mask);
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/*
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Handle the DFA (Dirty Flag Array) for determining which checkpoint contains the
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most recent mapping for an architectural register. This is needed to setup the
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SRAM address input for the RAT lookup.
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Structure:
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- Maintain a grid of bits (one row for each arch. reg, one column for each checkpoint).
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- Head/Tail pointer keep track of most recently/least recently allocated valid checkpoints.
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Operation:
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- When a new checkpoint is allocated for a branch or speculation point, we advance
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the head pointer and clear the entire DFA column for that checkpoint. For branches which
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write a register, the write should update the old checkpoint, not the newly allocated one.
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- When a register write operation comes through, update the row of the head checkpoint
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corresponding to the destination architectural register index.
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*/
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wire [`CHKPT_NUM-1:0] dfa_column_clear = allocated_chkpt;
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wire [`CHKPT_NUM-1:0] ds1_active_chkpt = (`CHKPT_NUM'h1 << chkpt_head_ptr);
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assign dfa_dirty_bit_ld = dfa_column_clear | // Clear newly allocated checkpoint
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(ds1_active_chkpt & {`CHKPT_NUM{ds1_dest_wr}}); // Update current checkpoint
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wire [`ARCH_REGS-1:0] ds1_dest_idx_vec = (1 << ds1_dest_idx);
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generate
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for (g=0; g<`CHKPT_NUM; g=g+1) begin : dfa_gen
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for (k=0; k<`ARCH_REGS; k=k+1) begin : dfa_dirty_bit_gen
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assign dfa_dirty_bit_in[g][k] = ~dfa_column_clear[g] & ((ds1_dest_idx_vec[k] & ds1_dest_wr) ? 1'b1 : dfa_dirty_bit[g][k]);
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MDFFLR #(1) dfa_dirty_bit_ff (clk, rst, dfa_dirty_bit_ld[g], 1'b0, dfa_dirty_bit_in[g][k], dfa_dirty_bit[g][k]);
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// generate a "row" version as well
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assign dfa_dirty_bit_row[k][g] = dfa_dirty_bit[g][k] & chkpt_valid_mask[g];
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end
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end
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endgenerate
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// Determine which checkpoint contains the most recent mapping for each source and the destination
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// TODO: For now, assume 4 checkpoints. Find a nice way to make this general.
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assign ds1_src1_chkpt = (chkpt_head_ptr == 2'h0) ? (dfa_dirty_bit_row[ds1_src1_idx][0] ? 2'h0 :
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dfa_dirty_bit_row[ds1_src1_idx][1] ? 2'h1 :
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dfa_dirty_bit_row[ds1_src1_idx][2] ? 2'h2 : 2'h3) :
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(chkpt_head_ptr == 2'h1) ? (dfa_dirty_bit_row[ds1_src1_idx][1] ? 2'h1 :
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dfa_dirty_bit_row[ds1_src1_idx][2] ? 2'h2 :
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dfa_dirty_bit_row[ds1_src1_idx][3] ? 2'h3 : 2'h0) :
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(chkpt_head_ptr == 2'h2) ? (dfa_dirty_bit_row[ds1_src1_idx][2] ? 2'h2 :
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dfa_dirty_bit_row[ds1_src1_idx][3] ? 2'h3 :
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dfa_dirty_bit_row[ds1_src1_idx][0] ? 2'h0 : 2'h1) :
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(dfa_dirty_bit_row[ds1_src1_idx][3] ? 2'h3 :
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dfa_dirty_bit_row[ds1_src1_idx][0] ? 2'h0 :
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dfa_dirty_bit_row[ds1_src1_idx][1] ? 2'h1 : 2'h2);
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assign ds1_src2_chkpt = (chkpt_head_ptr == 2'h0) ? (dfa_dirty_bit_row[ds1_src2_idx][0] ? 2'h0 :
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dfa_dirty_bit_row[ds1_src2_idx][1] ? 2'h1 :
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dfa_dirty_bit_row[ds1_src2_idx][2] ? 2'h2 : 2'h3) :
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(chkpt_head_ptr == 2'h1) ? (dfa_dirty_bit_row[ds1_src2_idx][1] ? 2'h1 :
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dfa_dirty_bit_row[ds1_src2_idx][2] ? 2'h2 :
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dfa_dirty_bit_row[ds1_src2_idx][3] ? 2'h3 : 2'h0) :
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(chkpt_head_ptr == 2'h2) ? (dfa_dirty_bit_row[ds1_src2_idx][2] ? 2'h2 :
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dfa_dirty_bit_row[ds1_src2_idx][3] ? 2'h3 :
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dfa_dirty_bit_row[ds1_src2_idx][0] ? 2'h0 : 2'h1) :
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(dfa_dirty_bit_row[ds1_src2_idx][3] ? 2'h3 :
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dfa_dirty_bit_row[ds1_src2_idx][0] ? 2'h0 :
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dfa_dirty_bit_row[ds1_src2_idx][1] ? 2'h1 : 2'h2);
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assign ds1_dest_chkpt = (chkpt_head_ptr == 2'h0) ? (dfa_dirty_bit_row[ds1_dest_idx][0] ? 2'h0 :
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dfa_dirty_bit_row[ds1_dest_idx][1] ? 2'h1 :
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dfa_dirty_bit_row[ds1_dest_idx][2] ? 2'h2 : 2'h3) :
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(chkpt_head_ptr == 2'h1) ? (dfa_dirty_bit_row[ds1_dest_idx][1] ? 2'h1 :
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dfa_dirty_bit_row[ds1_dest_idx][2] ? 2'h2 :
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dfa_dirty_bit_row[ds1_dest_idx][3] ? 2'h3 : 2'h0) :
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(chkpt_head_ptr == 2'h2) ? (dfa_dirty_bit_row[ds1_dest_idx][2] ? 2'h2 :
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dfa_dirty_bit_row[ds1_dest_idx][3] ? 2'h3 :
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dfa_dirty_bit_row[ds1_dest_idx][0] ? 2'h0 : 2'h1) :
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(dfa_dirty_bit_row[ds1_dest_idx][3] ? 2'h3 :
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dfa_dirty_bit_row[ds1_dest_idx][0] ? 2'h0 :
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dfa_dirty_bit_row[ds1_dest_idx][1] ? 2'h1 : 2'h2);
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// If no dirty bit set for any of the valid checkpoints, then committed copy must have latest mapping
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wire ds1_src1_use_rrat = ~(|dfa_dirty_bit_row[ds1_src1_idx]);
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wire ds1_src2_use_rrat = ~(|dfa_dirty_bit_row[ds1_src2_idx]);
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wire ds1_dest_use_rrat = ~(|dfa_dirty_bit_row[ds1_dest_idx]);
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// Generate the RAT SRAM read/write addresses and controls
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// Note: since tables are SRAM-based, we need to initialize the RRAT so that
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// registers are mapped correctly out of reset
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wire [`REG_IDX_SZ-1:0] map_table_init_ctr, map_table_init_ctr_in;
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wire map_table_init_in = map_table_init & (map_table_init_ctr != `ARCH_REGS);
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MDFFR #(1) map_table_init_ff (clk, rst, 1'b1, map_table_init_in, map_table_init);
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assign map_table_init_ctr_in = map_table_init_ctr + `REG_IDX_SZ'h1;
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MDFFLR #(`REG_IDX_SZ) map_table_init_ctr_ff (clk, rst, map_table_init, `REG_IDX_SZ'h0, map_table_init_ctr_in, map_table_init_ctr);
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wire [`REG_IDX_SZ+`CHKPT_PTR_SZ-1:0] ds1_rat_src1_rd_addr = {ds1_src1_idx,ds1_src1_chkpt};
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wire [`REG_IDX_SZ+`CHKPT_PTR_SZ-1:0] ds1_rat_src2_rd_addr = {ds1_src2_idx,ds1_src2_chkpt};
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wire [`REG_IDX_SZ+`CHKPT_PTR_SZ-1:0] ds1_rat_dest_rd_addr = {ds1_dest_idx,ds1_dest_chkpt};
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// Writes need to come from DS2 stage in case we read and write the same arch. register
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wire ds2_rat_wren, ds2_rat_wren_in;
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wire [`REG_IDX_SZ+`CHKPT_PTR_SZ-1:0] ds2_rat_wr_addr, ds2_rat_wr_addr_in;
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wire [`TAG_SZ-1:0] ds2_rat_wr_data;
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assign ds2_rat_wren_in = ds1_dest_wr;
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assign ds2_rat_wr_addr_in = {ds1_dest_idx,chkpt_head_ptr};
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MDFFR #(1) ds2_rat_wren_ff (clk, rst, 1'b0, ds2_rat_wren_in, ds2_rat_wren);
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244 |
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MDFFR #(`REG_IDX_SZ+`CHKPT_PTR_SZ) ds2_rat_wr_addr_ff (clk, rst, 1'b0, ds2_rat_wr_addr_in, ds2_rat_wr_addr);
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245 |
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assign ds2_rat_wr_data = ds2_dest_tag;
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246 |
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247 |
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wire [`TAG_SZ-1:0] ds2_rat_src1_rd_data, ds2_rrat_src1_rd_data;
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248 |
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wire [`TAG_SZ-1:0] ds2_rat_src2_rd_data, ds2_rrat_src2_rd_data;
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249 |
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wire [`TAG_SZ-1:0] ds2_rat_dest_rd_data, ds2_rrat_dest_rd_data;
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250 |
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|
251 |
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wire [`REG_IDX_SZ-1:0] ds_rrat_wr_addr = map_table_init ? map_table_init_ctr : rob_ds_ret_idx;
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252 |
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wire [`TAG_SZ-1:0] ds_rrat_wr_data = map_table_init ? map_table_init_ctr : rob_ds_ret_tag;
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253 |
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wire ds_rrat_wren = map_table_init | rob_ds_ret_valid & rob_ds_ret_dest_write;
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254 |
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|
255 |
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// Instantiate RAT SRAM blocks
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256 |
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// Note that we need 3 copies for the required 3 read ports (2 source operand tag reads, 1 previous dest tag read)
|
257 |
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// Read copy 1
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258 |
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dp_sram #(.DW(`TAG_SZ), .IW(`REG_IDX_SZ+`CHKPT_PTR_SZ)) rat0 (
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259 |
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.clk(clk),
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260 |
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.a_addr(ds1_rat_src1_rd_addr), // Read port
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261 |
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.a_dout(ds2_rat_src1_rd_data),
|
262 |
|
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|
263 |
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.b_addr(ds2_rat_wr_addr), // Write port
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264 |
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.b_wren(ds2_rat_wren),
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265 |
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.b_din(ds2_rat_wr_data)
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266 |
|
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);
|
267 |
|
|
|
268 |
|
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// Read copy 2
|
269 |
|
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dp_sram #(.DW(`TAG_SZ), .IW(`REG_IDX_SZ+`CHKPT_PTR_SZ)) rat1 (
|
270 |
|
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.clk(clk),
|
271 |
|
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.a_addr(ds1_rat_src2_rd_addr), // Read port
|
272 |
|
|
.a_dout(ds2_rat_src2_rd_data),
|
273 |
|
|
|
274 |
|
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.b_addr(ds2_rat_wr_addr), // Write port
|
275 |
|
|
.b_wren(ds2_rat_wren),
|
276 |
|
|
.b_din(ds2_rat_wr_data)
|
277 |
|
|
);
|
278 |
|
|
|
279 |
|
|
// Write copy 1
|
280 |
|
|
dp_sram #(.DW(`TAG_SZ), .IW(`REG_IDX_SZ+`CHKPT_PTR_SZ)) rat2 (
|
281 |
|
|
.clk(clk),
|
282 |
|
|
.a_addr(ds1_rat_dest_rd_addr), // Read port
|
283 |
|
|
.a_dout(ds2_rat_dest_rd_data),
|
284 |
|
|
|
285 |
|
|
.b_addr(ds2_rat_wr_addr), // Write port
|
286 |
|
|
.b_wren(ds2_rat_wren),
|
287 |
|
|
.b_din(ds2_rat_wr_data)
|
288 |
|
|
);
|
289 |
|
|
|
290 |
|
|
// Instantiate tables for the committed RAT copies
|
291 |
|
|
dp_sram #(.DW(`TAG_SZ), .IW(`REG_IDX_SZ)) rrat0 (
|
292 |
|
|
.clk(clk),
|
293 |
|
|
.a_addr(ds1_src1_idx), // Read port
|
294 |
|
|
.a_dout(ds2_rrat_src1_rd_data),
|
295 |
|
|
|
296 |
|
|
.b_addr(ds_rrat_wr_addr), // Write port (controlled by retire)
|
297 |
|
|
.b_wren(ds_rrat_wren),
|
298 |
|
|
.b_din(ds_rrat_wr_data)
|
299 |
|
|
);
|
300 |
|
|
dp_sram #(.DW(`TAG_SZ), .IW(`REG_IDX_SZ)) rrat1 (
|
301 |
|
|
.clk(clk),
|
302 |
|
|
.a_addr(ds1_src2_idx), // Read port
|
303 |
|
|
.a_dout(ds2_rrat_src2_rd_data),
|
304 |
|
|
|
305 |
|
|
.b_addr(ds_rrat_wr_addr), // Write port (controlled by retire)
|
306 |
|
|
.b_wren(ds_rrat_wren),
|
307 |
|
|
.b_din(ds_rrat_wr_data)
|
308 |
|
|
);
|
309 |
|
|
dp_sram #(.DW(`TAG_SZ), .IW(`REG_IDX_SZ)) rrat2 (
|
310 |
|
|
.clk(clk),
|
311 |
|
|
.a_addr(ds1_dest_idx), // Read port
|
312 |
|
|
.a_dout(ds2_rrat_dest_rd_data),
|
313 |
|
|
|
314 |
|
|
.b_addr(ds_rrat_wr_addr), // Write port (controlled by retire)
|
315 |
|
|
.b_wren(ds_rrat_wren),
|
316 |
|
|
.b_din(ds_rrat_wr_data)
|
317 |
|
|
);
|
318 |
|
|
|
319 |
|
|
// Since writes to map tables occur in DS2 stage, need to detect forwarding from previous instructions
|
320 |
|
|
wire ds1_src1_wr_fwd = (ds1_src1_idx == ds2_rat_wr_addr[`REG_IDX_SZ+`CHKPT_PTR_SZ-1:`CHKPT_PTR_SZ]) & ds2_rat_wren;
|
321 |
|
|
wire ds1_src2_wr_fwd = (ds1_src2_idx == ds2_rat_wr_addr[`REG_IDX_SZ+`CHKPT_PTR_SZ-1:`CHKPT_PTR_SZ]) & ds2_rat_wren;
|
322 |
|
|
wire ds1_dest_wr_fwd = (ds1_dest_idx == ds2_rat_wr_addr[`REG_IDX_SZ+`CHKPT_PTR_SZ-1:`CHKPT_PTR_SZ]) & ds2_rat_wren;
|
323 |
|
|
wire ds2_src1_wr_fwd, ds2_src2_wr_fwd, ds2_dest_wr_fwd;
|
324 |
|
|
MDFFR #(1) ds2_src1_wr_fwd_ff (clk, rst, 1'b0, ds1_src1_wr_fwd, ds2_src1_wr_fwd);
|
325 |
|
|
MDFFR #(1) ds2_src2_wr_fwd_ff (clk, rst, 1'b0, ds1_src2_wr_fwd, ds2_src2_wr_fwd);
|
326 |
|
|
MDFFR #(1) ds2_dest_wr_fwd_ff (clk, rst, 1'b0, ds1_dest_wr_fwd, ds2_dest_wr_fwd);
|
327 |
|
|
|
328 |
|
|
wire [`TAG_SZ-1:0] r_ds2_rat_wr_data;
|
329 |
|
|
wire r_ds2_wr_data_ld = ds2_rat_wren & (ds1_src1_wr_fwd | ds1_src2_wr_fwd | ds1_dest_wr_fwd);
|
330 |
|
|
MDFFL #(`TAG_SZ) r_ds2_rat_wr_data_ff (clk, r_ds2_wr_data_ld, ds2_rat_wr_data, r_ds2_rat_wr_data);
|
331 |
|
|
|
332 |
|
|
// Generate DS2 stage outputs
|
333 |
|
|
// Mux between RRAT and RAT outputs
|
334 |
|
|
MDFFL #(`CHKPT_PTR_SZ) ds2_chkpt_ptr_ff (clk, ds1_valid, chkpt_head_ptr, ds2_chkpt_ptr);
|
335 |
|
|
MDFFL #(`FL_PTR_SZ) ds2_fl_head_ptr_ff (clk, ds1_valid, ds1_fl_head_ptr, ds2_fl_head_ptr);
|
336 |
|
|
|
337 |
|
|
wire ds2_src1_use_rrat, ds2_src2_use_rrat, ds2_dest_use_rrat;
|
338 |
|
|
MDFFLR #(1) ds2_src1_use_rrat_ff (clk, rst, ds1_valid, 1'b0, ds1_src1_use_rrat, ds2_src1_use_rrat);
|
339 |
|
|
MDFFLR #(1) ds2_src2_use_rrat_ff (clk, rst, ds1_valid, 1'b0, ds1_src2_use_rrat, ds2_src2_use_rrat);
|
340 |
|
|
MDFFLR #(1) ds2_dest_use_rrat_ff (clk, rst, ds1_valid, 1'b0, ds1_dest_use_rrat, ds2_dest_use_rrat);
|
341 |
|
|
MDFFL #(`TAG_SZ) ds2_dest_tag_ff (clk, ds1_valid, ds1_dest_tag, ds2_dest_tag);
|
342 |
|
|
|
343 |
|
|
assign ds2_src1_tag = ds2_src1_wr_fwd ? r_ds2_rat_wr_data : ds2_src1_use_rrat ? ds2_rrat_src1_rd_data : ds2_rat_src1_rd_data;
|
344 |
|
|
assign ds2_src2_tag = ds2_src2_wr_fwd ? r_ds2_rat_wr_data : ds2_src2_use_rrat ? ds2_rrat_src2_rd_data : ds2_rat_src2_rd_data;
|
345 |
|
|
assign ds2_dest_tag_old = ds2_dest_wr_fwd ? r_ds2_rat_wr_data : ds2_dest_use_rrat ? ds2_rrat_dest_rd_data : ds2_rat_dest_rd_data;
|
346 |
|
|
|
347 |
|
|
|
348 |
|
|
|
349 |
|
|
|
350 |
|
|
endmodule
|