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madscienti |
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----------------------------------------------------------------------------
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-- Design Analysis --
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----------------------------------------------------------------------------
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Analyze pcore s3e_onewire_master ...
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----------------------------------------------------------------------------
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-- File Generation --
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----------------------------------------------------------------------------
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Creating HDL source directory ...
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| 12 |
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Generating top peripheral VHDL template ...
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| 13 |
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Generating stub user logic Verilog template ...
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HDL templates successfully generated ...
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| 15 |
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Creating data directory ...
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| 16 |
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Generating XPS inteface files ...
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WARNING:HDLParsers:3497 - Ignoring Verilog File
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"D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_onewire_mast
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er_v1_00_a/data/../hdl/verilog/user_logic.v"
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| 20 |
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Compiling vhdl file
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut
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4.vhd" in Library proc_common_v2_00_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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| 25 |
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Compiling vhdl file
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| 26 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_b
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it.vhd" in Library proc_common_v2_00_a.
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Entity compiled.
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| 29 |
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Entity (Architecture ) compiled.
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| 30 |
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Compiling vhdl file
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| 31 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit
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.vhd" in Library proc_common_v2_00_a.
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Entity compiled.
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| 34 |
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Entity (Architecture ) compiled.
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| 35 |
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Compiling vhdl file
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.v
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hd" in Library proc_common_v2_00_a.
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Entity compiled.
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| 39 |
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Entity (Architecture ) compiled.
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| 40 |
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Compiling vhdl file
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| 41 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_count
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er.vhd" in Library proc_common_v2_00_a.
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Entity compiled.
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| 44 |
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Entity (Architecture ) compiled.
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| 45 |
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Compiling vhdl file
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| 46 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_
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pkg.vhd" in Library proc_common_v2_00_a.
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| 48 |
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Package compiled.
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| 49 |
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Package body compiled.
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| 50 |
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Compiling vhdl file
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| 51 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_count
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er_top.vhd" in Library proc_common_v2_00_a.
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| 53 |
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Entity compiled.
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| 54 |
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Entity (Architecture ) compiled.
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| 55 |
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Compiling vhdl file
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| 56 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_t
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op.vhd" in Library proc_common_v2_00_a.
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| 58 |
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Entity compiled.
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| 59 |
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Entity (Architecture ) compiled.
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| 60 |
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Compiling vhdl file
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| 61 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd
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" in Library proc_common_v2_00_a.
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| 63 |
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Entity compiled.
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| 64 |
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Entity (Architecture ) compiled.
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| 65 |
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Compiling vhdl file
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| 66 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.
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| 67 |
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vhd" in Library proc_common_v2_00_a.
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| 68 |
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Entity compiled.
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| 69 |
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Entity (Architecture ) compiled.
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| 70 |
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Compiling vhdl file
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| 71 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd
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| 72 |
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" in Library proc_common_v2_00_a.
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| 73 |
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Entity compiled.
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| 74 |
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Entity (Architecture ) compiled.
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| 75 |
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Compiling vhdl file
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| 76 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd"
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| 77 |
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in Library proc_common_v2_00_a.
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| 78 |
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Package compiled.
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| 79 |
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Package body compiled.
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| 80 |
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Compiling vhdl file
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| 81 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd"
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| 82 |
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in Library proc_common_v2_00_a.
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| 83 |
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Entity compiled.
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| 84 |
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Entity (Architecture ) compiled.
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| 85 |
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Compiling vhdl file
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| 86 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd"
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| 87 |
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in Library proc_common_v2_00_a.
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| 88 |
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Entity compiled.
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| 89 |
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Entity (Architecture ) compiled.
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| 90 |
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Compiling vhdl file
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| 91 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vh
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| 92 |
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d" in Library proc_common_v2_00_a.
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| 93 |
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Entity compiled.
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| 94 |
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Entity (Architecture ) compiled.
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| 95 |
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Compiling vhdl file
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| 96 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_sel
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ect.vhd" in Library proc_common_v2_00_a.
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| 98 |
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Entity compiled.
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| 99 |
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Entity (Architecture ) compiled.
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| 100 |
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Compiling vhdl file
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| 101 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.v
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| 102 |
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hd" in Library proc_common_v2_00_a.
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| 103 |
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Entity compiled.
|
| 104 |
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Entity (Architecture ) compiled.
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| 105 |
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Compiling vhdl file
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| 106 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd"
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| 107 |
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in Library proc_common_v2_00_a.
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| 108 |
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Entity compiled.
|
| 109 |
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Entity (Architecture ) compiled.
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| 110 |
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Compiling vhdl file
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| 111 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd
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| 112 |
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" in Library proc_common_v2_00_a.
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| 113 |
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Entity compiled.
|
| 114 |
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Entity (Architecture ) compiled.
|
| 115 |
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Compiling vhdl file
|
| 116 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg
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| 117 |
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.vhd" in Library proc_common_v2_00_a.
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| 118 |
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Entity compiled.
|
| 119 |
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Entity (Architecture ) compiled.
|
| 120 |
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Compiling vhdl file
|
| 121 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.v
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| 122 |
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hd" in Library proc_common_v2_00_a.
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| 123 |
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Entity compiled.
|
| 124 |
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Entity (Architecture ) compiled.
|
| 125 |
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Compiling vhdl file
|
| 126 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter
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| 127 |
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.vhd" in Library proc_common_v2_00_a.
|
| 128 |
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Entity compiled.
|
| 129 |
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Entity (Architecture ) compiled.
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| 130 |
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Compiling vhdl file
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| 131 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd
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| 132 |
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" in Library proc_common_v2_00_a.
|
| 133 |
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Package compiled.
|
| 134 |
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Package body compiled.
|
| 135 |
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Compiling vhdl file
|
| 136 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.v
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| 137 |
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hd" in Library proc_common_v2_00_a.
|
| 138 |
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Entity compiled.
|
| 139 |
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Entity (Architecture ) compiled.
|
| 140 |
|
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Compiling vhdl file
|
| 141 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_
|
| 142 |
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cntr_ai.vhd" in Library proc_common_v2_00_a.
|
| 143 |
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Entity compiled.
|
| 144 |
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Entity (Architecture ) compiled.
|
| 145 |
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Compiling vhdl file
|
| 146 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd"
|
| 147 |
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in Library wrpfifo_v1_01_b.
|
| 148 |
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Entity compiled.
|
| 149 |
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Entity (Architecture ) compiled.
|
| 150 |
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Compiling vhdl file
|
| 151 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.
|
| 152 |
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vhd" in Library rdpfifo_v1_01_b.
|
| 153 |
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Entity compiled.
|
| 154 |
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Entity (Architecture ) compiled.
|
| 155 |
|
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Compiling vhdl file
|
| 156 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.
|
| 157 |
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vhd" in Library rdpfifo_v1_01_b.
|
| 158 |
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Entity compiled.
|
| 159 |
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Entity (Architecture ) compiled.
|
| 160 |
|
|
Compiling vhdl file
|
| 161 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.
|
| 162 |
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vhd" in Library wrpfifo_v1_01_b.
|
| 163 |
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Entity compiled.
|
| 164 |
|
|
Entity (Architecture ) compiled.
|
| 165 |
|
|
Compiling vhdl file
|
| 166 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.
|
| 167 |
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vhd" in Library wrpfifo_v1_01_b.
|
| 168 |
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Entity compiled.
|
| 169 |
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Entity (Architecture ) compiled.
|
| 170 |
|
|
Compiling vhdl file
|
| 171 |
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_c
|
| 172 |
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ntr.vhd" in Library opb_ipif_v3_01_c.
|
| 173 |
|
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Entity compiled.
|
| 174 |
|
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Entity (Architecture ) compiled.
|
| 175 |
|
|
Compiling vhdl file
|
| 176 |
|
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd"
|
| 177 |
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in Library opb_ipif_v3_01_c.
|
| 178 |
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Entity compiled.
|
| 179 |
|
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Entity (Architecture ) compiled.
|
| 180 |
|
|
Compiling vhdl file
|
| 181 |
|
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vh
|
| 182 |
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d" in Library opb_ipif_v3_01_c.
|
| 183 |
|
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Entity compiled.
|
| 184 |
|
|
Entity (Architecture ) compiled.
|
| 185 |
|
|
Compiling vhdl file
|
| 186 |
|
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd"
|
| 187 |
|
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in Library opb_ipif_v3_01_c.
|
| 188 |
|
|
Entity compiled.
|
| 189 |
|
|
Entity (Architecture ) compiled.
|
| 190 |
|
|
Compiling vhdl file
|
| 191 |
|
|
"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.
|
| 192 |
|
|
vhd" in Library opb_ipif_v3_01_c.
|
| 193 |
|
|
Entity compiled.
|
| 194 |
|
|
Entity (Architecture ) compiled.
|
| 195 |
|
|
Compiling vhdl file
|
| 196 |
|
|
"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_
|
| 197 |
|
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reg.vhd" in Library opb_ipif_v3_01_c.
|
| 198 |
|
|
Entity compiled.
|
| 199 |
|
|
Entity (Architecture ) compiled.
|
| 200 |
|
|
Compiling vhdl file
|
| 201 |
|
|
"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd"
|
| 202 |
|
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in Library opb_ipif_v3_01_c.
|
| 203 |
|
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Entity compiled.
|
| 204 |
|
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Entity (Architecture ) compiled.
|
| 205 |
|
|
Compiling vhdl file
|
| 206 |
|
|
"D:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interr
|
| 207 |
|
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upt_control.vhd" in Library interrupt_control_v1_00_a.
|
| 208 |
|
|
Entity compiled.
|
| 209 |
|
|
Entity (Architecture ) compiled.
|
| 210 |
|
|
Compiling vhdl file
|
| 211 |
|
|
"D:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd"
|
| 212 |
|
|
in Library wrpfifo_v1_01_b.
|
| 213 |
|
|
Entity compiled.
|
| 214 |
|
|
Entity (Architecture ) compiled.
|
| 215 |
|
|
Compiling vhdl file
|
| 216 |
|
|
"D:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd"
|
| 217 |
|
|
in Library rdpfifo_v1_01_b.
|
| 218 |
|
|
Entity compiled.
|
| 219 |
|
|
Entity (Architecture ) compiled.
|
| 220 |
|
|
Compiling vhdl file
|
| 221 |
|
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"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd" in
|
| 222 |
|
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Library opb_ipif_v3_01_c.
|
| 223 |
|
|
Entity compiled.
|
| 224 |
|
|
Entity (Architecture ) compiled.
|
| 225 |
|
|
Compiling vhdl file
|
| 226 |
|
|
"D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd"
|
| 227 |
|
|
in Library opb_ipif_v3_01_c.
|
| 228 |
|
|
Entity compiled.
|
| 229 |
|
|
Entity (Architecture ) compiled.
|
| 230 |
|
|
Compiling vhdl file
|
| 231 |
|
|
"D:/custom_pulse_generator/standalone_pulse_generator/pcores/s3e_onewire_master_
|
| 232 |
|
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v1_00_a/data/../hdl/vhdl/s3e_onewire_master.vhd" in Library
|
| 233 |
|
|
s3e_onewire_master_v1_00_a.
|
| 234 |
|
|
Entity compiled.
|
| 235 |
|
|
Entity (Architecture ) compiled.
|
| 236 |
|
|
|
| 237 |
|
|
|
| 238 |
|
|
Analyzing HDL attributes ...
|
| 239 |
|
|
INFO:MDT - IPTYPE set to value : PERIPHERAL
|
| 240 |
|
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INFO:MDT - IMP_NETLIST set to value : TRUE
|
| 241 |
|
|
INFO:MDT - HDL set to value : VHDL
|
| 242 |
|
|
WARNING:MDT - Unable to delete temparary XST project file
|
| 243 |
|
|
D:\custom_pulse_generator\standalone_pulse_generator\pcores\s3e_onewire_maste
|
| 244 |
|
|
r_v1_00_a\data\_s3e_onewire_master_xst.prj : 13
|
| 245 |
|
|
XPS interface files successfully generated ...
|
| 246 |
|
|
Creating development directory ...
|
| 247 |
|
|
Generating command option file ...
|
| 248 |
|
|
Generating readme file ...
|
| 249 |
|
|
Development misc files successfully generated ...
|
| 250 |
|
|
Creating projnav directory ...
|
| 251 |
|
|
Generating ProjNav support files ...
|
| 252 |
|
|
ProjNav support files successfully generated ...
|
| 253 |
|
|
Creating synthesis directory ...
|
| 254 |
|
|
Generating XST synthesis support files ...
|
| 255 |
|
|
XST synthesis support files successfully generated ...
|
| 256 |
|
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No BFM simulation files will be generated at this time ...
|
| 257 |
|
|
Creating software driver data directory ...
|
| 258 |
|
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Generating software driver XPS interface (mdd/tcl) files ...
|
| 259 |
|
|
Software driver data definition file (.mdd) successfully generated ...
|
| 260 |
|
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Software driver data generation file (.tcl) successfully generated ...
|
| 261 |
|
|
Creating software driver src directory ...
|
| 262 |
|
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Generating software driver template files ...
|
| 263 |
|
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Software driver compile file (Makefile) successfully generated ...
|
| 264 |
|
|
output user slave register(s) offset to software driver header ...
|
| 265 |
|
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output IPIF software reset/module identification register(s) offset to software
|
| 266 |
|
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driver header ...
|
| 267 |
|
|
Software driver header file (.h) successfully generated ...
|
| 268 |
|
|
Software driver source file (.c) successfully generated ...
|
| 269 |
|
|
Software driver SelfTest file (.c) successfully generated ...
|
| 270 |
|
|
Software driver template files successfully generated ...
|
| 271 |
|
|
|
| 272 |
|
|
----------------------------------------------------------------------------
|
| 273 |
|
|
-- Final Report --
|
| 274 |
|
|
----------------------------------------------------------------------------
|
| 275 |
|
|
Thank you for using Create and Import Peripheral Wizard! Please find your
|
| 276 |
|
|
peripheral hardware templates under
|
| 277 |
|
|
D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_onewire_master_v
|
| 278 |
|
|
1_00_a and peripheral software templates under
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D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_onewire_master_
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v1_00_a respectively.
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Peripheral Summary:
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top name : s3e_onewire_master
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version : 1.00.a
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type : OPB slave
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features : slave attachement
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mir/rst register
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user s/w registers
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Address Block Summary:
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user logic slv : C_BASEADDR + 0x00000000
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: C_BASEADDR + 0x000000FF
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mir/reset reg : C_BASEADDR + 0x00000100
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: C_BASEADDR + 0x000001FF
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File Summary
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- HDL source -
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D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_onewire_master_v
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1_00_a/hdl
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top entity : vhdl/s3e_onewire_master.vhd
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user logic : verilog/user_logic.v
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- XPS interface -
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D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_onewire_master_v
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1_00_a/data
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mpd : s3e_onewire_master_v2_1_0.mpd
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pao : s3e_onewire_master_v2_1_0.pao
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- ISE project -
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D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_onewire_master_v
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1_00_a/devl/projnav
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ise project : s3e_onewire_master.npl
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cli command : s3e_onewire_master.cli
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- XST synthesis -
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D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_onewire_master_v
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1_00_a/devl/synthesis
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xst script : s3e_onewire_master_xst.scr
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xst project : s3e_onewire_master_xst.prj
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- Misc file -
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D:\custom_pulse_generator\standalone_pulse_generator/pcores/s3e_onewire_master_v
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1_00_a/devl
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help : README.txt
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option : ipwiz.opt
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log : ipwiz.log
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- Driver source -
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D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_onewire_master_
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v1_00_a/src
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makefile : Makefile
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header : s3e_onewire_master.h
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source : s3e_onewire_master.c
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selftest : s3e_onewire_master_selftest.c
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- Driver interface -
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D:\custom_pulse_generator\standalone_pulse_generator/drivers/s3e_onewire_master_
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v1_00_a/data
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mdd : s3e_onewire_master_v2_1_0.mdd
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tcl : s3e_onewire_master_v2_1_0.tcl
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