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rehnmaak |
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USB 1.1 / 2.0 serial data transfer core
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-----------------------------------------
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Version: 2009-10-06
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Author: Joris van Rantwijk
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Language: VHDL
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License: GPL - GNU General Public License
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Website: http://www.xs4all.nl/~rjoris/fpga/usb.html
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usb_serial is a synthesizable VHDL core, implementing serial data
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transfer over USB. Combined with a UTMI-compatible USB transceiver
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chip, this core acts as a USB device that transfers a byte stream
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in both directions over the bus.
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This package is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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-----------------------------------------
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See MANUAL.pdf for detailed information.
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-----------------------------------------
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Files in this package
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---------------------
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COPYING Text of the GNU General Public License.
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MANUAL.pdf Manual for usb_serial core.
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Makefile Script to synthesizes the VHDL code for Xilinx devices.
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usb_serial.vhdl Main core.
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usb_control.vhdl Sub-entity handling control requests.
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usb_init.vhdl Sub-entity handling device initialization.
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usb_packet.vhdl Sub-entity for sending and receiving packets.
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usb_transact.vhdl Sub-entity for transaction handling.
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usbtest.vhdl Sample top-level design for testing.
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te0146.ucf Constraints file for a TE0146 FPGA module.
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testdev.py Python program running a torture test on usbtest.bit.
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perftest.c C program measuring data transfer performance on Linux.
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crcformula.py Python program for computing CRC update formulas.
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----
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The rest of this file contains some unorganized notitions.
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Changes from version 2007-04-19 to 2009-10-06
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---------------------------------------------
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* usb_init:
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+ Add generic HSSUPPORT
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+ Rename USBRST to I_USBRST
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+ Add output signal I_HIGHSPEED, active iff attached in high speed mode
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+ Add output signal I_SUSPEND, active iff suspended by host
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+ Add output P_CHIRPK
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+ Add output PHY_XCVRSELECT
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+ Add output PHY_TERMSELECT
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+ Implement HS handshake / FS fallback protocol.
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+ Implement suspend detection.
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* usb_packet:
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+ Add input P_CHIRPK.
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+ Send continuous chirp-K when P_CHIRPK asserted.
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+ Use signal s_dataout instead of variable v_dataout as register.
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+ Recognize PING as a valid token packet.
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+ Clear PHY_TXVALID and PHY_DATAOUT in response to RESET.
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+ Pay attention to PHY_RXERROR while receiving handshake packet.
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+ Eliminate ST_RFIN state and release P_RXACT one cycle earlier,
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i.e. at the same time as raising P_RXFIN. (Necessary because PHY_RXACTIVE
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may be low for just a single cycle between packets).
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* usb_transact:
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+ Verified that releasing P_RXACT while asserting P_RXFIN is handled fine.
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+ Add generic HSSUPPORT.
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+ Add output signal T_PING.
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+ Add input signal T_NYET; must be valid when SEND goes down.
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+ Eliminate ST_FIN so that we will always be in time to catch the rising
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edge of P_RXACT even in the cycle immediately following P_RXFIN.
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+ Implement PING transaction (same application timing as IN transaction).
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+ Implement NYET handshake.
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+ Reduce guaranteed decision time for application from 10 to 2 cycles.
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+ Separate inter-packet delay and response timeout values for FS and HS;
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increase FS inter-packet delay from 10 to 14 cycles.
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+ Ignore our own transmitted packet while waiting for ACK.
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+ Fail transaction if empty packet received while waiting for ACK or DATA.
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+ Again rejected (after extensive consideration) the idea of using
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PHY_LINESTATE for inter-packet delay, even though this is actually
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required according to the UTMI standard. It is difficult to reliably
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relate PHY_LINESTATE to logical send/receive activity. The best I can come
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up with is to have an inter-packet timer which counts down iff the line
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is idle as indicated by PHY_LINESTATE. But detecting line idle in FS mode
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depends on the SE0-to-J transition, which makes the scheme vulnerable in
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case the SE0 state is missed somehow.
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So we stay with the concept of inter-packet timing based on PHY_RXACTIVE
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plus a much relaxed timeout for host responses.
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Note to self: please don't waste more time on this.
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* usb_control:
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+ Add generic HSSUPPORT.
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+ Rename upstream interface signals to C_xxx.
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+ Add input signal T_PING (ignored, therefore always ACK-ed).
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+ Add output signal T_NYET (always driven to zero).
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+ Redesigned descriptor ROM interface.
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+ Implement ENDPOINT_HALT feature.
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+ Implement self-powered bit in status word.
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* usb_serial:
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+ Changed interface to sub-entities.
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+ Redesigned descriptor ROM interface.
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+ Implement device_qualifier and other_speed_configuration descriptors.
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+ Split single block RAM into three separate RAMs for RX buffer,
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TX buffer and descriptor ROM.
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+ Streamline state machine.
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+ Implement PING / NYET handshake.
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+ Add RXLEN / TXROOM status signals.
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+ Add TXCORK control signal.
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+ Add HIGHSPEED and SUSPEND signals to application interface.
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+ Prepare for separate clock domains.
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+ Support halting of endpoints.
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* usb_serial_wb:
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+ Removed. Wishbone is not intended for this kind of thing.
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* usbtest:
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+ Add testing of TXCORK flag.
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+ Add blast mode for test of fast streaming transmission.
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* Makefile:
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+ Fix command line options for newer versions of Xilinx tools.
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* testdev.py:
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+ Testing of TXCORK feature.
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+ Adapt test parameters for bigger TX/RX buffers in the device.
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+ Test partial read of incoming data.
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* perftest.c
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+ Performance measurements.
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Performance measurements
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------------------------
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Version 20090929:
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Performance full speed, RX 128, TX 128, libusb-1.0 async:
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RX 67108864 bytes in 61.673 s = 1088137 bytes/s
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TX 64000000 bytes in 58.816 s = 1088146 bytes/s
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Performance high speed, RX 2k, TX 1k, libusb-1.0 async:
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RX 67108864 bytes in 1.490 s = 45049302 bytes/s
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TX 64000000 bytes in 1.953 s = 32766457 bytes/s
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Intermediate version 20090917:
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( Comparing performance of normal code against error injection. )
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Performance FS, normal:
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RX 67108864 bytes in 61.674 s = 1088118 bytes/s
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TX 64000000 bytes in 58.820 s = 1088073 bytes/s
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Performance HS, normal:
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RX 67108864 bytes in 1.535 s = 43727704 bytes/s
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TX 64000000 bytes in 1.961 s = 32635212 bytes/s
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Performance FS, error injection:
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RX 67108864 bytes in 82.163 s = 816777 bytes/s
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TX 64000000 bytes in 78.420 s = 816113 bytes/s
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Performance HS, error injection:
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RX 67108864 bytes in 1.965 s = 34144882 bytes/s
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TX 64000000 bytes in 3.110 s = 20576099 bytes/s
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Tested
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------
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+ Suspend/resume with SUSPEND signal used as clock gate.
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+ Verified that none of the following events occur during functional test:
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aborted transaction; duplicate OUT packet; OUT-NAK in high speed mode.
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+ Deliberate error injection: works ok, but reduced performance as expected.
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+ Tested SetFeature(ENDPOINT_HALT)
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+ Functional test and performance test:
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+ full speed, konijn, linux, RX 128, TX 128
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+ full speed, konijn, linux, RX 128, TX 128, no_fullpacket
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+ full speed, konijn, linux, RX 1k, TX 128
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+ full speed, konijn, linux, RX 128, TX 1k (one time hang in perftest)
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+ full speed, konijn, linux, RX 2k, TX 1k
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+ high speed, konijn, linux, RX 1k, TX 1k (problems with usbserial, fixed)
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+ high speed, konijn, linux, RX 2k, TX 1k
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+ high speed, konijn, linux, RX 2k, TX 1k, no_fullpacket
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+ high speed, konijn, linux, RX 1k, TX 2k
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+ high speed, konijn, linux, RX 4k, TX 2k
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+ full speed, schildpad, linux, RX 128, TX 128
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+ fallback to full speed, schildpad, linux, RX 2k, TX 1k
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+ full speed, sron, linux
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+ high speed, sron, linux
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+ Limited functional test:
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+ full speed, schildpad, Win2k, RX 128, TX 128 (fails due to zero length packet)
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+ full speed, schildpad, Win2k, RX 128, TX 128, no_fullpacket
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+ fallback to full speed, schildpad, Win2k, RX 2k, TX 1k, no_fullpacket (failed)
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+ full speed, iBook, RX 128, TX 128
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+ high speed, iBook, RX 2k, TX 1k
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+ full speed, sron, Windows XP
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+ high speed, sron, Windows XP
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+ Performance:
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+ full speed, konijn, linux, RX 128, TX 128
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+ high speed, konijn, linux, RX 2k, TX 1k
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+ Verify descriptors, device, config, qualifier, other_speed_config, status:
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+ full speed, konijn, linux
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+ high speed, konijn, linux
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+ Test suspend/resume:
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+ full speed, konijn
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+ full speed, iBook
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+ high speed, konijn
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+ high speed, iBook
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+ Plug-in handling:
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+ high speed, konijn, linux
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+ fallback to full speed, schildpad, linux
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+ high speed, sron, Windows XP
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+ high speed, iBook
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Misc issues
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-----------
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* USB 2.0 high speed requires support of SET_FEATURE(TEST_MODE).
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We will not implement this.
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Reason: overkill, no way to test it properly.
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* Suspend detection is implemented.
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The output signal SUSPEND from usb_serial can be used to combinatorially
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drive the suspend pin on the UTMI interface. Reset of the SUSPEND signal
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is asynchronous and can therefore work even when the FPGA has no clock.
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* We will not implement detection of SOF packets.
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Reason: usefulness is questionable.
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* No separate clock domains.
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Reason: difficult to implement, very hard to validate.
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* There is a problem with empty packets under Windows 2000.
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The Windows 2000 version of usbser.dll chokes on unexpected empty packets,
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such as send by the device after a final full-length packet.
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This has been solved in Windows XP.
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* A babble error occurs when a device sends more bytes than expected
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by the host, even if this is less than the maximum packet size.
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This may happen if software submits an IN request which is not
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a multiple of the maximum packet size. It may also happen if the host
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sends an invalid standard device request, for example GET_STATUS with
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wLength=0.
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To avoid this, always submit IN requests with the transfer size set to
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a multiple of the maximum packet size.
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Note that babble errors can freeze the host controller; this is a known
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bug of VIA UHCI controllers:
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http://www.mail-archive.com/linux-usb-devel@lists.sourceforge.net/msg17019.html
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* After plugging in, the Linux kernel log shows
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"device descriptor read/64, error -62" and
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"Cannot enable port 2. Maybe the USB cable is bad?".
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After the errors, the kernel retries and the second attempt is successful.
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It seems pretty reproducible; occurs in FS and HS mode after plugin,
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but not after soft-reattach of the device.
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It is worse under Win2k; the USB subsystem seems to crash after plugging in.
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Theory: Initialization of the FPGA initialization takes longer than 100 ms,
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causing us to miss the initial port handshake.
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* Even 8k TX buffer is not sufficient for loss-free transmission @ 25 MB/s.
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Loss rate becomes much higher under CPU load.
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FPGA Resources
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| 276 |
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--------------
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( From mapper log file; target = XC3S1000 )
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Design: usbtest-20070419
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Tools: Xilinx Webpack 7.1i
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Number of errors: 0
|
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Number of warnings: 2
|
| 285 |
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Logic Utilization:
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| 286 |
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Number of Slice Flip Flops: 301 out of 15,360 1%
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| 287 |
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Number of 4 input LUTs: 969 out of 15,360 6%
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Logic Distribution:
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Number of occupied Slices: 573 out of 7,680 7%
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Number of Slices containing only related logic: 573 out of 573 100%
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Number of Slices containing unrelated logic: 0 out of 573 0%
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*See NOTES below for an explanation of the effects of unrelated logic
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Total Number 4 input LUTs: 1,034 out of 15,360 6%
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Number used as logic: 969
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Number used as a route-thru: 65
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Number of bonded IOBs: 31 out of 173 17%
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IOB Flip Flops: 27
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Number of Block RAMs: 2 out of 24 8%
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Number of GCLKs: 1 out of 8 12%
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Total equivalent gate count for design: 140,539
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----
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Design: usbtest-20090927, full speed, RX 128, TX 128
|
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Tools: Xilinx Webpack 7.1i
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Number of errors: 0
|
| 309 |
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Number of warnings: 2
|
| 310 |
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Logic Utilization:
|
| 311 |
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Number of Slice Flip Flops: 337 out of 15,360 2%
|
| 312 |
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Number of 4 input LUTs: 1,151 out of 15,360 7%
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Logic Distribution:
|
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Number of occupied Slices: 671 out of 7,680 8%
|
| 315 |
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Number of Slices containing only related logic: 671 out of 671 100%
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Number of Slices containing unrelated logic: 0 out of 671 0%
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*See NOTES below for an explanation of the effects of unrelated logic
|
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Total Number 4 input LUTs: 1,249 out of 15,360 8%
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Number used as logic: 1,151
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Number used as a route-thru: 98
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Number of bonded IOBs: 31 out of 173 17%
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IOB Flip Flops: 31
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Number of Block RAMs: 4 out of 24 16%
|
| 324 |
|
|
Number of GCLKs: 1 out of 8 12%
|
| 325 |
|
|
|
| 326 |
|
|
Total equivalent gate count for design: 273,110
|
| 327 |
|
|
|
| 328 |
|
|
----
|
| 329 |
|
|
|
| 330 |
|
|
Design: usbtest-20090929, high speed, RX 2k, TX 1k
|
| 331 |
|
|
Tools: Xilinx Webpack 7.1i
|
| 332 |
|
|
|
| 333 |
|
|
Number of errors: 0
|
| 334 |
|
|
Number of warnings: 2
|
| 335 |
|
|
Logic Utilization:
|
| 336 |
|
|
Number of Slice Flip Flops: 380 out of 15,360 2%
|
| 337 |
|
|
Number of 4 input LUTs: 1,349 out of 15,360 8%
|
| 338 |
|
|
Logic Distribution:
|
| 339 |
|
|
Number of occupied Slices: 787 out of 7,680 10%
|
| 340 |
|
|
Number of Slices containing only related logic: 787 out of 787 100%
|
| 341 |
|
|
Number of Slices containing unrelated logic: 0 out of 787 0%
|
| 342 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 343 |
|
|
Total Number 4 input LUTs: 1,465 out of 15,360 9%
|
| 344 |
|
|
Number used as logic: 1,349
|
| 345 |
|
|
Number used as a route-thru: 116
|
| 346 |
|
|
Number of bonded IOBs: 31 out of 173 17%
|
| 347 |
|
|
IOB Flip Flops: 34
|
| 348 |
|
|
Number of Block RAMs: 4 out of 24 16%
|
| 349 |
|
|
Number of GCLKs: 1 out of 8 12%
|
| 350 |
|
|
|
| 351 |
|
|
Total equivalent gate count for design: 274,894
|
| 352 |
|
|
|
| 353 |
|
|
----
|
| 354 |
|
|
|
| 355 |
|
|
Design: usb_serial only, 20090929, full speex RX 128, TX 128
|
| 356 |
|
|
Tools: Xilinx Webpack 7.1i
|
| 357 |
|
|
|
| 358 |
|
|
Number of errors: 0
|
| 359 |
|
|
Number of warnings: 2
|
| 360 |
|
|
Logic Utilization:
|
| 361 |
|
|
Number of Slice Flip Flops: 235 out of 15,360 1%
|
| 362 |
|
|
Number of 4 input LUTs: 841 out of 15,360 5%
|
| 363 |
|
|
Logic Distribution:
|
| 364 |
|
|
Number of occupied Slices: 479 out of 7,680 6%
|
| 365 |
|
|
Number of Slices containing only related logic: 479 out of 479 100%
|
| 366 |
|
|
Number of Slices containing unrelated logic: 0 out of 479 0%
|
| 367 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 368 |
|
|
Total Number 4 input LUTs: 899 out of 15,360 5%
|
| 369 |
|
|
Number used as logic: 841
|
| 370 |
|
|
Number used as a route-thru: 58
|
| 371 |
|
|
Number of bonded IOBs: 69 out of 173 39%
|
| 372 |
|
|
IOB Flip Flops: 33
|
| 373 |
|
|
Number of Block RAMs: 3 out of 24 12%
|
| 374 |
|
|
Number of GCLKs: 1 out of 8 12%
|
| 375 |
|
|
|
| 376 |
|
|
Total equivalent gate count for design: 204,527
|
| 377 |
|
|
|
| 378 |
|
|
----
|
| 379 |
|
|
|
| 380 |
|
|
Design: usb_serial only, 20090929, high speed, RX 2k, TX 1k
|
| 381 |
|
|
Tools: Xilinx Webpack 7.1i
|
| 382 |
|
|
|
| 383 |
|
|
Number of errors: 0
|
| 384 |
|
|
Number of warnings: 2
|
| 385 |
|
|
Logic Utilization:
|
| 386 |
|
|
Number of Slice Flip Flops: 285 out of 15,360 1%
|
| 387 |
|
|
Number of 4 input LUTs: 1,062 out of 15,360 6%
|
| 388 |
|
|
Logic Distribution:
|
| 389 |
|
|
Number of occupied Slices: 610 out of 7,680 7%
|
| 390 |
|
|
Number of Slices containing only related logic: 610 out of 610 100%
|
| 391 |
|
|
Number of Slices containing unrelated logic: 0 out of 610 0%
|
| 392 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 393 |
|
|
Total Number 4 input LUTs: 1,139 out of 15,360 7%
|
| 394 |
|
|
Number used as logic: 1,062
|
| 395 |
|
|
Number used as a route-thru: 77
|
| 396 |
|
|
Number of bonded IOBs: 76 out of 173 43%
|
| 397 |
|
|
IOB Flip Flops: 36
|
| 398 |
|
|
Number of Block RAMs: 3 out of 24 12%
|
| 399 |
|
|
Number of GCLKs: 1 out of 8 12%
|
| 400 |
|
|
|
| 401 |
|
|
Total equivalent gate count for design: 206,559
|
| 402 |
|
|
|
| 403 |
|
|
----
|
| 404 |
|
|
|
| 405 |
|
|
Design: usb_serial only, 20090929, full speed, RX 128, TX 128
|
| 406 |
|
|
Tools: Xilinx ISE 11.2
|
| 407 |
|
|
|
| 408 |
|
|
Number of errors: 0
|
| 409 |
|
|
Number of warnings: 1
|
| 410 |
|
|
Logic Utilization:
|
| 411 |
|
|
Number of Slice Flip Flops: 227 out of 15,360 1%
|
| 412 |
|
|
Number of 4 input LUTs: 808 out of 15,360 5%
|
| 413 |
|
|
Logic Distribution:
|
| 414 |
|
|
Number of occupied Slices: 459 out of 7,680 5%
|
| 415 |
|
|
Number of Slices containing only related logic: 459 out of 459 100%
|
| 416 |
|
|
Number of Slices containing unrelated logic: 0 out of 459 0%
|
| 417 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic.
|
| 418 |
|
|
Total Number of 4 input LUTs: 835 out of 15,360 5%
|
| 419 |
|
|
Number used as logic: 808
|
| 420 |
|
|
Number used as a route-thru: 27
|
| 421 |
|
|
The Slice Logic Distribution report is not meaningful if the design is
|
| 422 |
|
|
over-mapped for a non-slice resource or if Placement fails.
|
| 423 |
|
|
Number of bonded IOBs: 69 out of 173 39%
|
| 424 |
|
|
IOB Flip Flops: 27
|
| 425 |
|
|
Number of RAMB16s: 3 out of 24 12%
|
| 426 |
|
|
Number of BUFGMUXs: 1 out of 8 12%
|
| 427 |
|
|
|
| 428 |
|
|
----
|
| 429 |
|
|
|
| 430 |
|
|
Design: usb_serial only, 20090929, high speed, RX 2k, TX 1k
|
| 431 |
|
|
Tools: Xilinx ISE 11.2
|
| 432 |
|
|
|
| 433 |
|
|
Number of errors: 0
|
| 434 |
|
|
Number of warnings: 2
|
| 435 |
|
|
Logic Utilization:
|
| 436 |
|
|
Number of Slice Flip Flops: 265 out of 15,360 1%
|
| 437 |
|
|
Number of 4 input LUTs: 955 out of 15,360 6%
|
| 438 |
|
|
Logic Distribution:
|
| 439 |
|
|
Number of occupied Slices: 555 out of 7,680 7%
|
| 440 |
|
|
Number of Slices containing only related logic: 555 out of 555 100%
|
| 441 |
|
|
Number of Slices containing unrelated logic: 0 out of 555 0%
|
| 442 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic.
|
| 443 |
|
|
Total Number of 4 input LUTs: 1,010 out of 15,360 6%
|
| 444 |
|
|
Number used as logic: 955
|
| 445 |
|
|
Number used as a route-thru: 55
|
| 446 |
|
|
The Slice Logic Distribution report is not meaningful if the design is
|
| 447 |
|
|
over-mapped for a non-slice resource or if Placement fails.
|
| 448 |
|
|
Number of bonded IOBs: 76 out of 173 43%
|
| 449 |
|
|
IOB Flip Flops: 32
|
| 450 |
|
|
Number of RAMB16s: 3 out of 24 12%
|
| 451 |
|
|
Number of BUFGMUXs: 1 out of 8 12%
|
| 452 |
|
|
|
| 453 |
|
|
----
|
