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rehnmaak |
--
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-- USB 2.0 Initialization, handshake and reset detection.
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--
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-- This entity provides the following functions:
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--
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-- * USB bus attachment: At powerup and after a RESET signal, switch to
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-- non-driving mode, wait for 17 ms, then attach to the USB bus. This
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-- should ensure that the host notices our reattachment and initiates
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-- a reset procedure.
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--
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-- * High speed handshake (if HSSUPPORT enabled): attempt to enter
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-- high speed mode after a bus reset.
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--
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-- * Monitor the linestate for reset and/or suspend signalling.
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--
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-- The low-level interface connects to an UTMI compliant USB PHY such as
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-- the SMSC GT3200. The UTMI interface must be configured for 60 MHz operation
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-- with an 8-bit data bus.
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--
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library ieee;
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use ieee.std_logic_1164.all, ieee.numeric_std.all;
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entity usb_init is
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generic (
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-- Support high speed mode.
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HSSUPPORT : boolean := false );
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port (
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-- 60 MHz UTMI clock.
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CLK : in std_logic;
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-- Synchronous reset; triggers detach and reattach to the USB bus.
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RESET : in std_logic;
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-- High for one clock if a reset signal is detected on the USB bus.
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I_USBRST : out std_logic;
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-- High when attached to the host in high speed mode.
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I_HIGHSPEED : out std_logic;
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-- High when suspended.
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-- Reset of this signal is asynchronous.
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-- This signal may be used to drive (inverted) the UTMI SuspendM pin.
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I_SUSPEND : out std_logic;
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-- High to tell usb_packet that it must drive a continuous K state.
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P_CHIRPK : out std_logic;
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-- Connect to the UTMI Reset signal.
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PHY_RESET : out std_logic;
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-- Connect to the UTMI LineState signal.
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PHY_LINESTATE : in std_logic_vector(1 downto 0);
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-- Cconnect to the UTMI OpMode signal.
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PHY_OPMODE : out std_logic_vector(1 downto 0);
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-- Connect to the UTMI XcvrSelect signal (0 = high speed, 1 = full speed).
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PHY_XCVRSELECT : out std_logic;
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-- Connect to the UTMI TermSelect signal (0 = high speed, 1 = full speed).
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PHY_TERMSELECT : out std_logic );
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end entity usb_init;
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architecture usb_init_arch of usb_init is
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-- Time from bus idle until device suspend (3 ms).
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constant TIME_SUSPEND : unsigned(19 downto 0) := to_unsigned(180000, 20);
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-- Time from start of SE0 until detection of reset signal (2.5 us + 10%).
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constant TIME_RESET : unsigned(7 downto 0) := to_unsigned(165, 8);
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-- Time to wait for good SE0 when waking up from suspend (6 ms).
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constant TIME_SUSPRST: unsigned(19 downto 0) := to_unsigned(360000, 20);
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-- Duration of chirp K from device during high speed detection (1 ms + 10%).
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constant TIME_CHIRPK : unsigned(19 downto 0) := to_unsigned(66000, 20);
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-- Minimum duration of chirp J/K during high speed detection (2.5 us + 10%).
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constant TIME_FILT : unsigned(7 downto 0) := to_unsigned(165, 8);
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-- Time to wait for chirp until giving up (1.1 ms).
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constant TIME_WTFS : unsigned(19 downto 0) := to_unsigned(66000, 20);
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-- Time to wait after reverting to full-speed before sampling the bus (100 us).
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constant TIME_WTRSTHS : unsigned(19 downto 0) := to_unsigned(6000, 20);
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-- State machine
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type t_state is (
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ST_INIT, ST_FSRESET, ST_FULLSPEED, ST_SUSPEND, ST_SUSPRESET,
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ST_SENDCHIRP, ST_RECVCHIRP, ST_HIGHSPEED, ST_HSREVERT );
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signal s_state : t_state := ST_INIT;
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-- Timers.
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signal s_timer1 : unsigned(7 downto 0);
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signal s_timer2 : unsigned(19 downto 0) := to_unsigned(0, 20);
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-- Count J/K chirps.
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signal s_chirpcnt : unsigned(2 downto 0);
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-- High if the device is operating in high speed (or suspended from high speed).
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signal s_highspeed : std_logic := '0';
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-- High if the device is currently suspended.
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-- Reset of this signal is asynchronous.
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signal s_suspend : std_logic := '0';
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-- Input registers.
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signal s_linestate : std_logic_vector(1 downto 0);
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-- Output registers.
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signal s_reset : std_logic := '1';
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signal s_opmode : std_logic_vector(1 downto 0) := "01";
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signal s_xcvrselect : std_logic := '1';
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signal s_termselect : std_logic := '1';
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signal s_chirpk : std_logic := '0';
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begin
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I_USBRST <= s_reset;
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I_HIGHSPEED <= s_highspeed;
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I_SUSPEND <= s_suspend;
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P_CHIRPK <= s_chirpk;
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PHY_RESET <= s_reset;
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PHY_OPMODE <= s_opmode;
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PHY_XCVRSELECT <= s_xcvrselect;
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PHY_TERMSELECT <= s_termselect;
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-- Synchronous process.
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process is
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variable v_clrtimer1 : std_logic;
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variable v_clrtimer2 : std_logic;
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begin
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wait until rising_edge(CLK);
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-- By default, do not clear the timers.
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v_clrtimer1 := '0';
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v_clrtimer2 := '0';
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-- Register linestate input.
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s_linestate <= PHY_LINESTATE;
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-- Default assignments to registers.
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s_reset <= '0';
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s_chirpk <= '0';
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if RESET = '1' then
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-- Reset PHY.
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s_reset <= '1';
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s_opmode <= "01";
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s_xcvrselect <= '1';
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s_termselect <= '1';
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-- Go to ST_INIT state and wait until bus attachment.
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v_clrtimer1 := '1';
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v_clrtimer2 := '1';
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s_highspeed <= '0';
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s_state <= ST_INIT;
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else
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case s_state is
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when ST_INIT =>
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-- Wait before attaching to bus.
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s_opmode <= "01"; -- non-driving
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s_xcvrselect <= '1'; -- full speed
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s_termselect <= '1'; -- full speed
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v_clrtimer1 := '1';
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if s_timer2 = to_unsigned(0, s_timer2'length) - 1 then
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-- Timer2 overflows after ~ 17 ms; attach to bus.
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v_clrtimer2 := '1';
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s_state <= ST_FULLSPEED;
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end if;
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when ST_FSRESET =>
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-- Waiting for end of reset before full speed operation.
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s_highspeed <= '0';
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s_opmode <= "00"; -- normal
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s_xcvrselect <= '1'; -- full speed
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s_termselect <= '1'; -- full speed
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v_clrtimer1 := '1';
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v_clrtimer2 := '1';
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if s_linestate /= "00" then
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-- Reset signal ended.
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s_state <= ST_FULLSPEED;
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end if;
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when ST_FULLSPEED =>
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-- Operating in full speed.
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s_highspeed <= '0';
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s_opmode <= "00"; -- normal
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s_xcvrselect <= '1'; -- full speed
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s_termselect <= '1'; -- full speed
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if s_linestate /= "00" then
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-- Bus not in SE0 state; clear reset timer.
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v_clrtimer1 := '1';
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end if;
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if s_linestate /= "01" then
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-- Bus not in J state; clear suspend timer.
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v_clrtimer2 := '1';
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end if;
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if s_timer1 = TIME_RESET then
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-- Bus has been in SE0 state for TIME_RESET;
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-- this is a reset signal.
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s_reset <= '1';
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if HSSUPPORT then
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s_state <= ST_SENDCHIRP;
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else
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s_state <= ST_FSRESET;
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end if;
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elsif s_timer2 = TIME_SUSPEND then
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-- Bus has been idle for TIME_SUSPEND;
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-- go to suspend state.
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s_state <= ST_SUSPEND;
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end if;
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when ST_SUSPEND =>
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-- Suspended; waiting for resume signal.
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-- Possibly our clock will be disabled; wake up
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-- is initiated by the asynchronous reset of s_suspend.
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s_opmode <= "00"; -- normal
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s_xcvrselect <= '1'; -- full speed
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s_termselect <= '1'; -- full speed
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v_clrtimer1 := '1';
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v_clrtimer2 := '1';
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if s_linestate /= "01" then
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-- Bus not in J state; resume.
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if HSSUPPORT and s_highspeed = '1' then
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-- High speed resume protocol.
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if s_linestate = "10" then
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-- Bus in K state; resume to high speed.
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s_state <= ST_HIGHSPEED;
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elsif s_linestate = "00" then
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-- Bus in SE0 state; start reset detection.
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s_state <= ST_SUSPRESET;
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end if;
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else
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-- Resume to full speed.
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s_state <= ST_FULLSPEED;
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end if;
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end if;
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when ST_SUSPRESET =>
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-- Wake up in SE0 state; wait for proper reset signal.
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s_opmode <= "00"; -- normal
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s_xcvrselect <= '1'; -- full speed
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s_termselect <= '1'; -- full speed
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if s_linestate /= "00" then
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-- Bus not in SE0 state; clear reset timer.
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v_clrtimer1 := '1';
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end if;
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if s_timer1 = TIME_RESET then
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-- Bus has been in SE0 state for TIME_RESET;
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-- this is a reset signal.
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s_reset <= '1';
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v_clrtimer2 := '1';
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s_state <= ST_SENDCHIRP;
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end if;
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if s_timer2 = TIME_SUSPRST then
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-- Still no proper reset signal; go back to sleep.
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s_state <= ST_SUSPEND;
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end if;
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when ST_SENDCHIRP =>
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-- Sending chirp K for a duration of TIME_CHIRPK.
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s_highspeed <= '0';
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s_opmode <= "10"; -- disable bit stuffing
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s_xcvrselect <= '0'; -- high speed
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s_termselect <= '1'; -- full speed
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s_chirpk <= '1'; -- send chirp K
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v_clrtimer1 := '1';
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if s_timer2 = TIME_CHIRPK then
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-- end of chirp K
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v_clrtimer2 := '1';
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s_chirpcnt <= "000";
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s_state <= ST_RECVCHIRP;
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end if;
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when ST_RECVCHIRP =>
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-- Waiting for K-J-K-J-K-J chirps.
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-- Note: DO NOT switch Opmode to normal yet; there
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-- may be pending bits in the transmission buffer.
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s_opmode <= "10"; -- disable bit stuffing
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s_xcvrselect <= '0'; -- high speed
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s_termselect <= '1'; -- full speed
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if ( s_chirpcnt(0) = '0' and s_linestate /= "10" ) or
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( s_chirpcnt(0) = '1' and s_linestate /= "01" ) then
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-- Not the linestate we want.
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v_clrtimer1 := '1';
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end if;
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if s_timer2 = TIME_WTFS then
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-- High speed detection failed; go to full speed.
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v_clrtimer1 := '1';
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v_clrtimer2 := '1';
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s_state <= ST_FSRESET;
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elsif s_timer1 = TIME_FILT then
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-- We got the chirp we wanted.
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if s_chirpcnt = 5 then
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-- This was the last chirp;
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-- we got a successful high speed handshake.
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v_clrtimer2 := '1';
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s_state <= ST_HIGHSPEED;
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end if;
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s_chirpcnt <= s_chirpcnt + 1;
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v_clrtimer1 := '1';
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end if;
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when ST_HIGHSPEED =>
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-- Operating in high speed.
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s_highspeed <= '1';
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s_opmode <= "00"; -- normal
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s_xcvrselect <= '0'; -- high speed
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s_termselect <= '0'; -- high speed
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if s_linestate /= "00" then
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-- Bus not idle; clear revert timer.
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v_clrtimer2 := '1';
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end if;
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if s_timer2 = TIME_SUSPEND then
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-- Bus has been idle for TIME_SUSPEND;
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-- revert to full speed.
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v_clrtimer2 := '1';
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s_state <= ST_HSREVERT;
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end if;
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when ST_HSREVERT =>
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-- Revert to full speed and wait for 100 us.
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s_opmode <= "00"; -- normal
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s_xcvrselect <= '1'; -- full speed
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s_termselect <= '1'; -- full speed
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if s_timer2 = TIME_WTRSTHS then
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v_clrtimer2 := '1';
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if s_linestate = "00" then
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-- Reset from high speed.
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s_reset <= '1';
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s_state <= ST_SENDCHIRP;
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else
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-- Suspend from high speed.
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s_state <= ST_SUSPEND;
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end if;
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end if;
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349 |
|
|
end case;
|
350 |
|
|
|
351 |
|
|
end if;
|
352 |
|
|
|
353 |
|
|
-- Increment or clear timer1.
|
354 |
|
|
if v_clrtimer1 = '1' then
|
355 |
|
|
s_timer1 <= to_unsigned(0, s_timer1'length);
|
356 |
|
|
else
|
357 |
|
|
s_timer1 <= s_timer1 + 1;
|
358 |
|
|
end if;
|
359 |
|
|
|
360 |
|
|
-- Increment or clear timer2.
|
361 |
|
|
if v_clrtimer2 = '1' then
|
362 |
|
|
s_timer2 <= to_unsigned(0, s_timer2'length);
|
363 |
|
|
else
|
364 |
|
|
s_timer2 <= s_timer2 + 1;
|
365 |
|
|
end if;
|
366 |
|
|
|
367 |
|
|
end process;
|
368 |
|
|
|
369 |
|
|
-- Drive the s_suspend flipflop (synchronous set, asynchronous reset).
|
370 |
|
|
process (CLK, PHY_LINESTATE) is
|
371 |
|
|
begin
|
372 |
|
|
if PHY_LINESTATE /= "01" then
|
373 |
|
|
-- The bus is not in full speed idle state;
|
374 |
|
|
-- reset the s_suspend flipflop.
|
375 |
|
|
s_suspend <= '0';
|
376 |
|
|
elsif rising_edge(CLK) then
|
377 |
|
|
if s_state = ST_SUSPEND then
|
378 |
|
|
-- Bus is idle and FSM is in suspend state;
|
379 |
|
|
-- enable the s_suspend flipflop.
|
380 |
|
|
s_suspend <= '1';
|
381 |
|
|
end if;
|
382 |
|
|
end if;
|
383 |
|
|
end process;
|
384 |
|
|
|
385 |
|
|
end architecture usb_init_arch;
|
386 |
|
|
|