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[/] [opb_usblite/] [trunk/] [refdesign/] [data/] [system.ucf] - Blame information for rev 8

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Line No. Rev Author Line
1 8 rehnmaak 
#  Spartan-3E Starter Board
2 
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<0> LOC=F9  |  IOSTANDARD = LVCMOS33;
3 
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<1> LOC=E9  |  IOSTANDARD = LVCMOS33;
4 
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<2> LOC=D11  |  IOSTANDARD = LVCMOS33;
5 
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<3> LOC=C11  |  IOSTANDARD = LVCMOS33;
6 
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<4> LOC=F11  |  IOSTANDARD = LVCMOS33;
7 
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<5> LOC=E11  |  IOSTANDARD = LVCMOS33;
8 
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<6> LOC=E12  |  IOSTANDARD = LVCMOS33;
9 
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<7> LOC=F12  |  IOSTANDARD = LVCMOS33;
10 
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<0> LOC=N17 | PULLDOWN  |  IOSTANDARD = LVCMOS33;
11 
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<1> LOC=H18 | PULLDOWN  |  IOSTANDARD = LVCMOS33;
12 
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<2> LOC=L14 | PULLDOWN  |  IOSTANDARD = LVCMOS33;
13 
Net fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin<3> LOC=L13 | PULLDOWN  |  IOSTANDARD = LVCMOS33;
14 
Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<0> LOC=D18 | PULLDOWN  |  IOSTANDARD = LVCMOS33;
15 
Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<1> LOC=H13 | PULLDOWN  |  IOSTANDARD = LVCMOS33;
16 
Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<2> LOC=V4 | PULLDOWN  |  IOSTANDARD = LVCMOS33;
17 
Net fpga_0_Buttons_4Bit_GPIO_IO_I_pin<3> LOC=V16 | PULLDOWN  |  IOSTANDARD = LVCMOS33;
18 
Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=J5  |  IOSTANDARD = DIFF_SSTL2_I;
19 
Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=J4  |  IOSTANDARD = DIFF_SSTL2_I;
20 
Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=K3  |  IOSTANDARD = SSTL2_I;
21 
Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=K4  |  IOSTANDARD = SSTL2_I;
22 
Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=C1  |  IOSTANDARD = SSTL2_I;
23 
Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=C2  |  IOSTANDARD = SSTL2_I;
24 
Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=D1  |  IOSTANDARD = SSTL2_I;
25 
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=K5  |  IOSTANDARD = SSTL2_I;
26 
Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=K6  |  IOSTANDARD = SSTL2_I;
27 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=T1  |  IOSTANDARD = SSTL2_I;
28 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=R3  |  IOSTANDARD = SSTL2_I;
29 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=R2  |  IOSTANDARD = SSTL2_I;
30 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=P1  |  IOSTANDARD = SSTL2_I;
31 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=F4  |  IOSTANDARD = SSTL2_I;
32 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=H4  |  IOSTANDARD = SSTL2_I;
33 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=H3  |  IOSTANDARD = SSTL2_I;
34 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=H1  |  IOSTANDARD = SSTL2_I;
35 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=H2  |  IOSTANDARD = SSTL2_I;
36 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=N4  |  IOSTANDARD = SSTL2_I;
37 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=T2  |  IOSTANDARD = SSTL2_I;
38 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=N5  |  IOSTANDARD = SSTL2_I;
39 
Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=P2  |  IOSTANDARD = SSTL2_I;
40 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<0> LOC=L2  |  IOSTANDARD = SSTL2_I  |  PULLUP;
41 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<1> LOC=L1  |  IOSTANDARD = SSTL2_I  |  PULLUP;
42 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<2> LOC=L3  |  IOSTANDARD = SSTL2_I  |  PULLUP;
43 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<3> LOC=L4  |  IOSTANDARD = SSTL2_I  |  PULLUP;
44 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<4> LOC=M3  |  IOSTANDARD = SSTL2_I  |  PULLUP;
45 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<5> LOC=M4  |  IOSTANDARD = SSTL2_I  |  PULLUP;
46 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<6> LOC=M5  |  IOSTANDARD = SSTL2_I  |  PULLUP;
47 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<7> LOC=M6  |  IOSTANDARD = SSTL2_I  |  PULLUP;
48 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<8> LOC=E2  |  IOSTANDARD = SSTL2_I  |  PULLUP;
49 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<9> LOC=E1  |  IOSTANDARD = SSTL2_I  |  PULLUP;
50 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<10> LOC=F1  |  IOSTANDARD = SSTL2_I  |  PULLUP;
51 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<11> LOC=F2  |  IOSTANDARD = SSTL2_I  |  PULLUP;
52 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<12> LOC=G6  |  IOSTANDARD = SSTL2_I  |  PULLUP;
53 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<13> LOC=G5  |  IOSTANDARD = SSTL2_I  |  PULLUP;
54 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<14> LOC=H6  |  IOSTANDARD = SSTL2_I  |  PULLUP;
55 
Net fpga_0_DDR_SDRAM_DDR_DQ_pin<15> LOC=H5  |  IOSTANDARD = SSTL2_I  |  PULLUP;
56 
Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=J2  |  IOSTANDARD = SSTL2_I;
57 
Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=J1  |  IOSTANDARD = SSTL2_I;
58 
Net fpga_0_DDR_SDRAM_DDR_DQS_pin<0> LOC=L6  |  IOSTANDARD = SSTL2_I;
59 
Net fpga_0_DDR_SDRAM_DDR_DQS_pin<1> LOC=G3  |  IOSTANDARD = SSTL2_I  |  PULLUP;
60 
Net fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin LOC=P13  |  IOSTANDARD = LVCMOS33;
61 
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
62 
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;
63 
Net fpga_0_clk_1_sys_clk_pin LOC=c9  |  IOSTANDARD = LVCMOS33;
64 
Net fpga_0_rst_1_sys_rst_pin TIG;
65 
Net fpga_0_rst_1_sys_rst_pin LOC=K17  |  IOSTANDARD = LVCMOS33  |  PULLDOWN;
66 
 
67 
NET opb_usblite_0_txdoe_pin LOC=B4 |  IOSTANDARD = LVCMOS33;
68 
NET opb_usblite_0_rxd_pin LOC=A4 |  IOSTANDARD = LVCMOS33;
69 
NET opb_usblite_0_rxdp_pin LOC=D5 |  IOSTANDARD = LVCMOS33;
70 
NET opb_usblite_0_rxdn_pin LOC=C5 |  IOSTANDARD = LVCMOS33;
71 
NET opb_usblite_0_txdp_pin LOC=A6 |  IOSTANDARD = LVCMOS33;
72 
NET opb_usblite_0_txdn_pin LOC=B6 |  IOSTANDARD = LVCMOS33;
73 
 
74 
###### DDR_SDRAM
75 
 
76 
############################################################################
77 
# Placement constraints for luts in tap delay ckt
78 
############################################################################
79 
 
80 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0"  RLOC=X0Y6;
81 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0"  U_SET = "tap_dly0_u_set";
82 
 
83 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" RLOC=X0Y6;
84 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1"  U_SET = "tap_dly0_u_set";
85 
 
86 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" RLOC=X0Y7;
87 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2"  U_SET = "tap_dly0_u_set";
88 
 
89 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" RLOC=X0Y7;
90 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3"  U_SET = "tap_dly0_u_set";
91 
 
92 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" RLOC=X1Y6;
93 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4"  U_SET = "tap_dly0_u_set";
94 
 
95 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" RLOC=X1Y6;
96 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5"  U_SET = "tap_dly0_u_set";
97 
 
98 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" RLOC=X1Y7;
99 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6"  U_SET = "tap_dly0_u_set";
100 
 
101 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" RLOC=X1Y7;
102 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7"  U_SET = "tap_dly0_u_set";
103 
 
104 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" RLOC=X0Y4;
105 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8"  U_SET = "tap_dly0_u_set";
106 
 
107 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" RLOC=X0Y4;
108 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9"  U_SET = "tap_dly0_u_set";
109 
 
110 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" RLOC=X0Y5;
111 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10"  U_SET = "tap_dly0_u_set";
112 
 
113 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" RLOC=X0Y5;
114 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11"  U_SET = "tap_dly0_u_set";
115 
 
116 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" RLOC=X1Y4;
117 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12"  U_SET = "tap_dly0_u_set";
118 
 
119 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" RLOC=X1Y4;
120 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13"  U_SET = "tap_dly0_u_set";
121 
 
122 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" RLOC=X1Y5;
123 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14"  U_SET = "tap_dly0_u_set";
124 
 
125 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" RLOC=X1Y5;
126 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15"  U_SET = "tap_dly0_u_set";
127 
 
128 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" RLOC=X0Y2;
129 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16"  U_SET = "tap_dly0_u_set";
130 
 
131 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" RLOC=X0Y2;
132 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17"  U_SET = "tap_dly0_u_set";
133 
 
134 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" RLOC=X0Y3;
135 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18"  U_SET = "tap_dly0_u_set";
136 
 
137 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" RLOC=X0Y3;
138 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19"  U_SET = "tap_dly0_u_set";
139 
 
140 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" RLOC=X1Y2;
141 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20"  U_SET = "tap_dly0_u_set";
142 
 
143 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" RLOC=X1Y2;
144 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21"  U_SET = "tap_dly0_u_set";
145 
 
146 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" RLOC=X1Y3;
147 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22"  U_SET = "tap_dly0_u_set";
148 
 
149 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" RLOC=X1Y3;
150 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23"  U_SET = "tap_dly0_u_set";
151 
 
152 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" RLOC=X0Y0;
153 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24"  U_SET = "tap_dly0_u_set";
154 
 
155 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" RLOC=X0Y0;
156 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25"  U_SET = "tap_dly0_u_set";
157 
 
158 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" RLOC=X0Y1;
159 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26"  U_SET = "tap_dly0_u_set";
160 
 
161 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" RLOC=X0Y1;
162 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27"  U_SET = "tap_dly0_u_set";
163 
 
164 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28" RLOC=X1Y0;
165 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28"  U_SET = "tap_dly0_u_set";
166 
 
167 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29" RLOC=X1Y0;
168 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29"  U_SET = "tap_dly0_u_set";
169 
 
170 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30" RLOC=X1Y1;
171 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30"  U_SET = "tap_dly0_u_set";
172 
 
173 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31" RLOC=X1Y1;
174 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31"  U_SET = "tap_dly0_u_set";
175 
 
176 
#######################################################################################################################
177 
# Placement constraints for first stage flops in tap delay ckt #
178 
#######################################################################################################################
179 
 
180 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[0].r"    RLOC=X0Y6;
181 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[0].r"   U_SET = "tap_dly0_u_set";
182 
 
183 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[1].r" RLOC=X0Y6;
184 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[1].r"  U_SET = "tap_dly0_u_set";
185 
 
186 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[2].r" RLOC=X0Y7;
187 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[2].r"  U_SET = "tap_dly0_u_set";
188 
 
189 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[3].r" RLOC=X0Y7;
190 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[3].r"  U_SET = "tap_dly0_u_set";
191 
 
192 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[4].r" RLOC=X1Y6;
193 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[4].r"  U_SET = "tap_dly0_u_set";
194 
 
195 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[5].r" RLOC=X1Y6;
196 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[5].r"  U_SET = "tap_dly0_u_set";
197 
 
198 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[6].r" RLOC=X1Y7;
199 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[6].r"  U_SET = "tap_dly0_u_set";
200 
 
201 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[7].r" RLOC=X1Y7;
202 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[7].r"  U_SET = "tap_dly0_u_set";
203 
 
204 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[8].r" RLOC=X0Y4;
205 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[8].r"  U_SET = "tap_dly0_u_set";
206 
 
207 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[9].r" RLOC=X0Y4;
208 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[9].r"  U_SET = "tap_dly0_u_set";
209 
 
210 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[10].r" RLOC=X0Y5;
211 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[10].r"  U_SET = "tap_dly0_u_set";
212 
 
213 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[11].r" RLOC=X0Y5;
214 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[11].r"  U_SET = "tap_dly0_u_set";
215 
 
216 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[12].r" RLOC=X1Y4;
217 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[12].r"  U_SET = "tap_dly0_u_set";
218 
 
219 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[13].r" RLOC=X1Y4;
220 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[13].r"  U_SET = "tap_dly0_u_set";
221 
 
222 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[14].r" RLOC=X1Y5;
223 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[14].r"  U_SET = "tap_dly0_u_set";
224 
 
225 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[15].r" RLOC=X1Y5;
226 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[15].r"  U_SET = "tap_dly0_u_set";
227 
 
228 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[16].r" RLOC=X0Y2;
229 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[16].r"  U_SET = "tap_dly0_u_set";
230 
 
231 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[17].r" RLOC=X0Y2;
232 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[17].r"  U_SET = "tap_dly0_u_set";
233 
 
234 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[18].r" RLOC=X0Y3;
235 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[18].r"  U_SET = "tap_dly0_u_set";
236 
 
237 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[19].r" RLOC=X0Y3;
238 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[19].r"  U_SET = "tap_dly0_u_set";
239 
 
240 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[20].r" RLOC=X1Y2;
241 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[20].r"  U_SET = "tap_dly0_u_set";
242 
 
243 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[21].r" RLOC=X1Y2;
244 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[21].r"  U_SET = "tap_dly0_u_set";
245 
 
246 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[22].r" RLOC=X1Y3;
247 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[22].r"  U_SET = "tap_dly0_u_set";
248 
 
249 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[23].r" RLOC=X1Y3;
250 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[23].r"  U_SET = "tap_dly0_u_set";
251 
 
252 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[24].r" RLOC=X0Y0;
253 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[24].r"  U_SET = "tap_dly0_u_set";
254 
 
255 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[25].r" RLOC=X0Y0;
256 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[25].r"  U_SET = "tap_dly0_u_set";
257 
 
258 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[26].r" RLOC=X0Y1;
259 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[26].r"  U_SET = "tap_dly0_u_set";
260 
 
261 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[27].r" RLOC=X0Y1;
262 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[27].r"  U_SET = "tap_dly0_u_set";
263 
 
264 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[28].r" RLOC=X1Y0;
265 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[28].r"  U_SET = "tap_dly0_u_set";
266 
 
267 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[29].r" RLOC=X1Y0;
268 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[29].r"  U_SET = "tap_dly0_u_set";
269 
 
270 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[30].r" RLOC=X1Y1;
271 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[30].r"  U_SET = "tap_dly0_u_set";
272 
 
273 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[31].r" RLOC=X1Y1;
274 
INST  "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.gen_tap1[31].r"  U_SET = "tap_dly0_u_set";
275 
 
276 
#######################################################################################################################
277 
# BEL constraints for luts in tap delay ckt #
278 
#######################################################################################################################
279 
 
280 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l0" BEL= G;
281 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l1" BEL= F;
282 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l2" BEL= G;
283 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l3" BEL= F;
284 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l4" BEL= G;
285 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l5" BEL= F;
286 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l6" BEL= G;
287 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l7" BEL= F;
288 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l8" BEL= G;
289 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l9" BEL= F;
290 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l10" BEL= G;
291 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l11" BEL= F;
292 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l12" BEL= G;
293 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l13" BEL= F;
294 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l14" BEL= G;
295 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l15" BEL= F;
296 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l16" BEL= G;
297 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l17" BEL= F;
298 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l18" BEL= G;
299 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l19" BEL= F;
300 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l20" BEL= G;
301 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l21" BEL= F;
302 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l22" BEL= G;
303 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l23" BEL= F;
304 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l24" BEL= G;
305 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l25" BEL= F;
306 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l26" BEL= G;
307 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l27" BEL= F;
308 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l28" BEL= G;
309 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l29" BEL= F;
310 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l30" BEL= G;
311 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/gen_no_sim.l31" BEL= F;
312 
 
313 
##############################################################################
314 
# Delay constraints
315 
##############################################################################
316 
 
317 
###### maxdelay of 400 ps will not be met. This constraint is just to get a better delay####
318 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[7]"  MAXDELAY = 400ps;
319 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[15]" MAXDELAY = 400ps;
320 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/tap[23]" MAXDELAY = 400ps;
321 
 
322 
###### maxdelay of 460 ps will not be met. This constraint is just to get a better delay####
323 
###### The reported delay will be in the range of 500 to 600 ps####
324 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dqs_int_delay_in*"                           MAXDELAY = 480ps;
325 
 
326 
###### maxdelay of 160 ps will not be met. This constraint is just to get a better delay####
327 
###### The reported delay will be in the range of 200 to 360 ps####
328 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[*]*u_dqs_delay_col*/delay*"  MAXDELAY = 200ps;
329 
 
330 
###################################################################################################
331 
######constraint to place flop1 and flop2 close togather for the calibration logic  ###############
332 
###################################################################################################
333 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/flop1[*]"               MAXDELAY = 3000ps;
334 
 
335 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/dqs_delayed_col*<*>"                         MAXDELAY = 1000ps;
336 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/rst_dqs_div"            MAXDELAY = 2500ps;
337 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed*"   MAXDELAY = 2000ps;
338 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/fifo*_wr_en<*>"                              MAXDELAY = 2000ps;
339 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/fifo_*_wr_addr_out<*><*>"          MAXDELAY = 2000ps;
340 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/fifo_*_data_out[*]"                MAXDELAY = 2000ps;
341 
NET "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dq<*>"                                                 MAXDELAY = 480ps;
342 
 
343 
#######################################################################################################################
344 
# Area Group Constraint For tap_dly and cal_ctl module #
345 
#######################################################################################################################
346 
 
347 
#INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/cal_ctl/*" AREA_GROUP = cal_ctl;
348 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/infrastructure/cal_top/tap_dly/*" AREA_GROUP = cal_ctl;
349 
#AREA_GROUP "cal_ctl" RANGE = SLICE_X0Y10:SLICE_X15Y23; // Old values
350 
AREA_GROUP "cal_ctl" RANGE = SLICE_X28Y70:SLICE_X39Y83;
351 
AREA_GROUP "cal_ctl" GROUP = CLOSED;
352 
 
353 
 
354 
##############################################################################
355 
# IOB and AREA constraints
356 
##############################################################################
357 
 
358 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/datapath_iobs/gen_dqs[*].dqs_iob*"    IOB = TRUE;
359 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/datapath_iobs/gen_dq[*].dq_iob*"      IOB = TRUE;
360 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_addr[*].addr_iob" IOB = TRUE;
361 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_ba[*].ba_iob"     IOB = TRUE;
362 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/gen_cke[*].cke_iob"   IOB = TRUE;
363 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/ras_iob"              IOB = TRUE;
364 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/cas_iob"              IOB = TRUE;
365 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/iobs/controller_iobs/we_iob"               IOB = TRUE;
366 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/dqs_div/dqs_rst_iob"                       IOB = TRUE;
367 
 
368 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[1]*u_fifo_bit"   LOC = SLICE_X2Y36;
369 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[1]*u_fifo_bit" LOC = SLICE_X2Y37;
370 
 
371 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[0]*u_fifo_bit"   LOC = SLICE_X0Y36;
372 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[0]*u_fifo_bit" LOC = SLICE_X0Y37;
373 
 
374 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[2]*u_fifo_bit"   LOC = SLICE_X2Y32;
375 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y33;
376 
 
377 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[3]*u_fifo_bit"   LOC = SLICE_X0Y32;
378 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y33;
379 
 
380 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[5]*u_fifo_bit"   LOC = SLICE_X2Y24;
381 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[5]*u_fifo_bit" LOC = SLICE_X2Y25;
382 
 
383 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[4]*u_fifo_bit"   LOC = SLICE_X0Y24;
384 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[4]*u_fifo_bit" LOC = SLICE_X0Y25;
385 
 
386 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[7]*u_fifo_bit"   LOC = SLICE_X0Y20;
387 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y21;
388 
 
389 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0/gen_data[6]*u_fifo_bit"   LOC = SLICE_X2Y20;
390 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[0]*strobe0_n/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y21;
391 
 
392 
 
393 
 
394 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[1]*u_fifo_bit"   LOC = SLICE_X0Y82;
395 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[1]*u_fifo_bit" LOC = SLICE_X0Y83;
396 
 
397 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[0]*u_fifo_bit"   LOC = SLICE_X2Y82;
398 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[0]*u_fifo_bit" LOC = SLICE_X2Y83;
399 
 
400 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[3]*u_fifo_bit"   LOC = SLICE_X0Y76;
401 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[3]*u_fifo_bit" LOC = SLICE_X0Y77;
402 
 
403 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[2]*u_fifo_bit"   LOC = SLICE_X2Y76;
404 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[2]*u_fifo_bit" LOC = SLICE_X2Y77;
405 
 
406 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[5]*u_fifo_bit"   LOC = SLICE_X0Y68;
407 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[5]*u_fifo_bit" LOC = SLICE_X0Y69;
408 
 
409 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[4]*u_fifo_bit"   LOC = SLICE_X2Y68;
410 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[4]*u_fifo_bit" LOC = SLICE_X2Y69;
411 
 
412 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[7]*u_fifo_bit"   LOC = SLICE_X0Y64;
413 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[7]*u_fifo_bit" LOC = SLICE_X0Y65;
414 
 
415 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0/gen_data[6]*u_fifo_bit"   LOC = SLICE_X2Y64;
416 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_data[1]*strobe0_n/gen_data[6]*u_fifo_bit" LOC = SLICE_X2Y65;
417 
 
418 
 
419 
 
420 
 
421 
#############################################################
422 
## DQS 0 Col 0
423 
#############################################################
424 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.one"   LOC = SLICE_X2Y29;
425 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.one"   BEL = F;
426 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.two"   LOC = SLICE_X2Y29;
427 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.two"   BEL = G;
428 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.three" LOC = SLICE_X2Y28;
429 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.three" BEL = G;
430 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.four"  LOC = SLICE_X2Y28;
431 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.four"  BEL = F;
432 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.five"  LOC = SLICE_X3Y29;
433 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.five"  BEL = G;
434 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.six"   LOC = SLICE_X3Y28;
435 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col0/gen_delay.six"   BEL = G;
436 
 
437 
#############################################################
438 
## DQS 0 Col 1
439 
#############################################################
440 
 
441 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.one"   LOC = SLICE_X0Y29;
442 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.one"   BEL = F;
443 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.two"   LOC = SLICE_X0Y29;
444 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.two"   BEL = G;
445 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.three" LOC = SLICE_X0Y28;
446 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.three" BEL = G;
447 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.four"  LOC = SLICE_X0Y28;
448 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.four"  BEL = F;
449 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.five"  LOC = SLICE_X1Y29;
450 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.five"  BEL = G;
451 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.six"   LOC = SLICE_X1Y28;
452 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]*u_dqs_delay_col1/gen_delay.six"   BEL = G;
453 
 
454 
#############################################################
455 
## DQS 1 Col 0
456 
#############################################################
457 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.one"   LOC = SLICE_X2Y73;
458 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.one"   BEL = F;
459 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.two"   LOC = SLICE_X2Y73;
460 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.two"   BEL = G;
461 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.three" LOC = SLICE_X2Y72;
462 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.three" BEL = G;
463 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.four"  LOC = SLICE_X2Y72;
464 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.four"  BEL = F;
465 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.five"  LOC = SLICE_X3Y73;
466 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.five"  BEL = G;
467 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.six"   LOC = SLICE_X3Y72;
468 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col0/gen_delay.six"   BEL = G;
469 
 
470 
#############################################################
471 
## DQS 1 Col 1
472 
#############################################################
473 
 
474 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.one"   LOC = SLICE_X0Y73;
475 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.one"   BEL = F;
476 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.two"   LOC = SLICE_X0Y73;
477 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.two"   BEL = G;
478 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.three" LOC = SLICE_X0Y72;
479 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.three" BEL = G;
480 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.four"  LOC = SLICE_X0Y72;
481 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.four"  BEL = F;
482 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.five"  LOC = SLICE_X1Y73;
483 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.five"  BEL = G;
484 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.six"   LOC = SLICE_X1Y72;
485 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]*u_dqs_delay_col1/gen_delay.six"   BEL = G;
486 
 
487 
#############################################################
488 
## WR ADDR 0
489 
#############################################################
490 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X1Y30;
491 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X1Y30;
492 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X1Y31;
493 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X1Y31;
494 
 
495 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X3Y30;
496 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X3Y30;
497 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X3Y31;
498 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X3Y31;
499 
 
500 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/*" LOC = SLICE_X1Y33;
501 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/*" LOC = SLICE_X3Y33;
502 
 
503 
#############################################################
504 
## WR ADDR 1
505 
#############################################################
506 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X1Y74;
507 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X1Y74;
508 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X1Y75;
509 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X1Y75;
510 
 
511 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit" LOC = SLICE_X3Y74;
512 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[1].u_addr_bit" LOC = SLICE_X3Y74;
513 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[2].u_addr_bit" LOC = SLICE_X3Y75;
514 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit" LOC = SLICE_X3Y75;
515 
 
516 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/*" LOC = SLICE_X1Y77;
517 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/*" LOC = SLICE_X3Y77;
518 
 
519 
#############################################################
520 
## DQS Loopback
521 
#############################################################
522 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.one"   LOC = SLICE_X0Y9;
523 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.one"   BEL = F;
524 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.two"   LOC = SLICE_X0Y8;
525 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.two"   BEL = F;
526 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.three" LOC = SLICE_X0Y9;
527 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.three" BEL = G;
528 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.four"  LOC = SLICE_X1Y8;
529 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.four"  BEL = F;
530 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.five"  LOC = SLICE_X1Y8;
531 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.five"  BEL = G;
532 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.six"   LOC = SLICE_X1Y9;
533 
INST "*/mpmc_core_0/gen_s3_ddr*.mpmc_phy_if_0/data_path/data_read_controller*rst_dqs_div_delayed/gen_delay.six"   BEL = G;
534 
 
535 
 
536 
 
537 
 

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