OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [Documents/] [CPU Instruction Set_files/] [sheet002.htm] - Blame information for rev 294

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 277 jshamlet
<html xmlns:o="urn:schemas-microsoft-com:office:office"
2 241 jshamlet
xmlns:x="urn:schemas-microsoft-com:office:excel"
3
xmlns="http://www.w3.org/TR/REC-html40">
4
 
5
<head>
6
<meta http-equiv=Content-Type content="text/html; charset=windows-1252">
7
<meta name=ProgId content=Excel.Sheet>
8
<meta name=Generator content="Microsoft Excel 12">
9
<link id=Main-File rel=Main-File href="../CPU%20Instruction%20Set.htm">
10
<link rel=File-List href=filelist.xml>
11
<link rel=Stylesheet href=stylesheet.css>
12
<style>
13
<!--table
14
        {mso-displayed-decimal-separator:"\.";
15
        mso-displayed-thousand-separator:"\,";}
16
@page
17
        {margin:.75in .7in .75in .7in;
18
        mso-header-margin:.3in;
19
        mso-footer-margin:.3in;}
20
-->
21
</style>
22
<![if !supportTabStrip]><script language="JavaScript">
23
<!--
24
function fnUpdateTabs()
25
 {
26
  if (parent.window.g_iIEVer>=4) {
27
   if (parent.document.readyState=="complete"
28
    && parent.frames['frTabs'].document.readyState=="complete")
29
   parent.fnSetActiveSheet(1);
30
  else
31
   window.setTimeout("fnUpdateTabs();",150);
32
 }
33
}
34
 
35
if (window.name!="frSheet")
36
 window.location.replace("../CPU%20Instruction%20Set.htm");
37
else
38
 fnUpdateTabs();
39
//-->
40
</script>
41
<![endif]>
42
</head>
43
 
44
<body link=blue vlink=purple>
45
 
46
<table border=0 cellpadding=0 cellspacing=0 width=1242 style='border-collapse:
47
 collapse;table-layout:fixed;width:932pt'>
48
 <col width=185 style='mso-width-source:userset;mso-width-alt:6765;width:139pt'>
49
 <col width=103 style='mso-width-source:userset;mso-width-alt:3766;width:77pt'>
50
 <col class=xl67 width=61 style='mso-width-source:userset;mso-width-alt:2230;
51
 width:46pt'>
52
 <col class=xl68 width=893 style='mso-width-source:userset;mso-width-alt:32658;
53
 width:670pt'>
54 272 jshamlet
 <tr height=35 style='height:26.25pt'>
55
  <td height=35 width=185 style='height:26.25pt;width:139pt'></td>
56 241 jshamlet
  <td width=103 style='width:77pt'></td>
57 272 jshamlet
  <td class=xl107 colspan=2 width=954 style='mso-ignore:colspan;width:716pt'>Open8
58 241 jshamlet
  CPU Core Generics</td>
59
 </tr>
60
 <tr height=20 style='height:15.0pt'>
61
  <td height=20 colspan=2 style='height:15.0pt;mso-ignore:colspan'></td>
62
  <td class=xl67></td>
63
  <td class=xl68></td>
64
 </tr>
65
 <tr height=20 style='height:15.0pt'>
66
  <td height=20 class=xl69 style='height:15.0pt'>Option</td>
67
  <td class=xl69>Argument Type</td>
68
  <td class=xl70>Default</td>
69
  <td class=xl72 width=893 style='width:670pt'>Description</td>
70
 </tr>
71
 <tr height=20 style='height:15.0pt'>
72
  <td height=20 class=xl76 style='height:15.0pt;border-top:none'>Program_Start_Addr</td>
73
  <td class=xl76 style='border-top:none;border-left:none'>16-bit Address</td>
74
  <td class=xl103 style='border-top:none;border-left:none'>x&quot;0000&quot;</td>
75
  <td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Initial
76
  program counter location</td>
77
 </tr>
78
 <tr height=20 style='height:15.0pt'>
79
  <td height=20 class=xl73 style='height:15.0pt;border-top:none'>ISR_Start_Addr</td>
80
  <td class=xl73 style='border-top:none;border-left:none'>16-bit Address</td>
81
  <td class=xl74 style='border-top:none;border-left:none'>x&quot;FFF0&quot;</td>
82
  <td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
83
  the initial location of the interrupt vector table</td>
84
 </tr>
85
 <tr height=20 style='height:15.0pt'>
86
  <td height=20 class=xl76 style='height:15.0pt;border-top:none'>Stack_Start_Addr</td>
87
  <td class=xl76 style='border-top:none;border-left:none'>16-bit Address</td>
88
  <td class=xl103 style='border-top:none;border-left:none'>x&quot;03FF&quot;</td>
89
  <td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Initial
90
  location of the CPU Stack - Must be located in accessible RAM</td>
91
 </tr>
92
 <tr height=40 style='height:30.0pt'>
93
  <td height=40 class=xl73 style='height:30.0pt;border-top:none'>Allow_Stack_Address_Move</td>
94
  <td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
95
  <td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
96
  <td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
97
  false, the RSP instruction will reset the stack pointer to
98
  &quot;Stack_Start_Addr&quot; by default. If true, the RSP instruction will
99
  either allow the stack pointer to be loaded from R1:R0 or copied to R1:R0
100 272 jshamlet
  depending on the status of the PSR_GP4 flag.</td>
101 241 jshamlet
 </tr>
102
 <tr height=80 style='height:60.0pt'>
103 272 jshamlet
  <td height=80 class=xl108 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td>
104
  <td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
105
  <td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
106
  <td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
107 241 jshamlet
  true, indexed instructions such as LDX, LDO, STX, STO will automatically
108
  increment if an odd register is specified. The effect is similar to a normal
109
  indexed instruction followed by an UPP instruction on the same register pair.
110
  For example, LDX R5 (or LDX R4++) will result in R0 getting the data stored
111
  at the address specified by R5:R4. Afterwards, the register pair R5:R4 will
112
  be incremented by 1. If false, specifying either register in a register pair
113
  will result in normal behavior.</td>
114
 </tr>
115
 <tr height=40 style='height:30.0pt'>
116 272 jshamlet
  <td height=40 class=xl73 style='height:30.0pt;border-top:none'>BRK_Implements_WAI</td>
117
  <td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
118
  <td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
119
  <td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
120 241 jshamlet
  true, the BRK instruction will cause the processor to halt as if an INT
121
  instruction was executed, but without triggering an interrupt. This is useful
122
  for pausing the CPU until an interrupt occurs. If false, the BRK instruction
123
  simply causes the CPU to execute 5 NOP cycles.</td>
124
 </tr>
125
 <tr height=20 style='height:15.0pt'>
126 272 jshamlet
  <td height=20 class=xl108 style='height:15.0pt;border-top:none'>Enable_NMI</td>
127
  <td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
128
  <td class=xl109 style='border-top:none;border-left:none'>TRUE</td>
129
  <td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Forces
130 241 jshamlet
  bit 0 of the Interrupt Mask to 1, causing Interrupt 0 to be non-maskable.</td>
131
 </tr>
132
 <tr height=40 style='height:30.0pt'>
133 272 jshamlet
  <td height=40 class=xl73 style='height:30.0pt;border-top:none'>Sequential_Interrupts</td>
134
  <td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
135
  <td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
136
  <td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Prohibits
137 241 jshamlet
  interrupts from initiating an ISR if the I-bit is set, making ISRs
138
  sequential. This potentially blocks interrupt priority by allowing a lower
139
  level interrupt to block a higher level interrupt. This can be fixed by
140
  clearing the I-bit in interruptable ISRs.</td>
141
 </tr>
142
 <tr height=40 style='height:30.0pt'>
143 272 jshamlet
  <td height=40 class=xl108 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td>
144
  <td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
145
  <td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
146
  <td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
147 241 jshamlet
  set, preserves the general purpose flags GP_PSR4 to GP_PSR7 on ISR exit,
148
  allowing them to be persistently set by interrupts. The lower four flag bits
149
  are always restored.</td>
150
 </tr>
151 272 jshamlet
 <tr height=40 style='height:30.0pt'>
152
  <td height=40 class=xl73 style='height:30.0pt;border-top:none'>Supervisor_Mode</td>
153
  <td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
154
  <td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
155
  <td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
156
  set to true, enables restrictions on RSP, CLP/STP, and SMSK where they only
157
  can alter internal registers if the I bit is set. Also initializes the CPU to
158
  start with the I-bit set. If set to false, there are no restrictions on these
159
  instructions.</td>
160
 </tr>
161 241 jshamlet
 <tr height=20 style='height:15.0pt'>
162 272 jshamlet
  <td height=20 class=xl108 style='height:15.0pt;border-top:none'>Unsigned_Index_Offsets</td>
163
  <td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
164
  <td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
165
  <td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Determines
166
  whether the offset calculation for LDO/STO is signed or unsigned. Default
167
  behavior is signed.</td>
168
 </tr>
169
 <tr height=20 style='height:15.0pt'>
170
  <td height=20 class=xl73 style='height:15.0pt;border-top:none'>Default_Interrupt_Mask</td>
171
  <td class=xl73 style='border-top:none;border-left:none'>8-bit Data</td>
172
  <td class=xl74 style='border-top:none;border-left:none'>x&quot;FF&quot;</td>
173
  <td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
174 241 jshamlet
  the initial interrupt mask (note that bit 0 is ignored, as this is the NMI)</td>
175
 </tr>
176
 <tr height=20 style='height:15.0pt'>
177 272 jshamlet
  <td height=20 class=xl108 style='height:15.0pt;border-top:none'>Clock_Frequency</td>
178
  <td class=xl108 style='border-top:none;border-left:none'>Real</td>
179
  <td class=xl109 style='border-top:none;border-left:none'>-</td>
180
  <td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Clock
181 241 jshamlet
  frequency in Hz of the CPU clock. Used to configure the 1Mhz/1uSec tick pulse</td>
182
 </tr>
183
 <![if supportMisalignedColumns]>
184
 <tr height=0 style='display:none'>
185
  <td width=185 style='width:139pt'></td>
186
  <td width=103 style='width:77pt'></td>
187
  <td width=61 style='width:46pt'></td>
188
  <td width=893 style='width:670pt'></td>
189
 </tr>
190
 <![endif]>
191
</table>
192
 
193
</body>
194
 
195
</html>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.