| 1 |
178 |
jshamlet |
----------------------------------------------
|
| 2 |
|
|
Open8 uRISC Assembly language description
|
| 3 |
|
|
----------------------------------------------
|
| 4 |
|
|
|
| 5 |
|
|
|
| 6 |
|
|
--------------------
|
| 7 |
|
|
Hardware information
|
| 8 |
|
|
--------------------
|
| 9 |
|
|
|
| 10 |
|
|
The CPU has 8 8-bit general purpose registers available,
|
| 11 |
|
|
R0-R7. In some operations, one register is paired with the
|
| 12 |
|
|
next one so they behave like a 16-bit register.
|
| 13 |
|
|
|
| 14 |
|
|
R0 is a special register, in that it is always the second
|
| 15 |
|
|
unstated operand in commands that work with 2 values (ie.
|
| 16 |
|
|
ADD R3 adds together R3 and R0), It also recieves the
|
| 17 |
|
|
results of most commands that have results (ie. ADD R3
|
| 18 |
|
|
stores the result of R0+R3 in R0).
|
| 19 |
|
|
|
| 20 |
|
|
There are 4 normally used state flags. The Zero flag,
|
| 21 |
|
|
the Carry flag, the Negative flag, and the Interrupt
|
| 22 |
|
|
Enable flag. The Negative, Zero, and Carry flags are
|
| 23 |
|
|
set/reset whenever any operation is carried out on ANY
|
| 24 |
|
|
register. Ie. If you decrement R3 and it reaches zero,
|
| 25 |
|
|
the Zero flag gets set. There are also 4 other General
|
| 26 |
|
|
Purpose flags whose setting and checking is left up to
|
| 27 |
|
|
you if you choose to use them.
|
| 28 |
|
|
|
| 29 |
|
|
These flags are implemented in a bit of memory called
|
| 30 |
|
|
the Program Status Register, or PSR.
|
| 31 |
|
|
|
| 32 |
|
|
There's also a program counter, as you'd expect, but you
|
| 33 |
|
|
can't access it's value from any of the opcodes, directly
|
| 34 |
|
|
or otherwise. That fact, and the lack of a BRanch Always
|
| 35 |
|
|
command, makes it tough to write easily relocateable
|
| 36 |
|
|
code.
|
| 37 |
|
|
|
| 38 |
|
|
--------------
|
| 39 |
|
|
OPCODE LISTING
|
| 40 |
|
|
--------------
|
| 41 |
|
|
|
| 42 |
|
|
Opcode Description [Example]
|
| 43 |
|
|
------------------------------------------------------------------
|
| 44 |
|
|
INC R0-07 | Increment Register [INC R4]
|
| 45 |
|
|
ADC R0-07 | R0=R#+R0 using carry flag [ADC R4]
|
| 46 |
|
|
TX0 R0-R7 | R0=R# [TX0 R2]
|
| 47 |
|
|
OR R0-R7 | R0=R0|R# [OR R6]
|
| 48 |
|
|
AND R0-R7 | R0=R0&R# [AND R4]
|
| 49 |
|
|
CLR R0 | Clears R0 [CLR R0]
|
| 50 |
|
|
XOR R0-R7 | R0=R0^R# [XOR R2]
|
| 51 |
|
|
ROL R0-R7 | R#=R#<<1. Roll R# Left [ROL R2]
|
| 52 |
|
|
ROR R0-R7 | R#=R#>>1. Roll R# Right [ROR R2]
|
| 53 |
|
|
DEC R0-R7 | R#=R#-1 [DEC R4]
|
| 54 |
|
|
SBC R0-R7 | R0=R0-R# using carry flag [SBC R6]
|
| 55 |
|
|
ADD R0-R7 | R0=R0+R# [ADD R3]
|
| 56 |
|
|
MUL R0-R7 | R1:R0 = Rn * R0
|
| 57 |
|
|
STP PSR_Z | Set Zero flag [STP PSR_Z]
|
| 58 |
|
|
STP PSR_C | Set Carry flag [STP PSR_C]
|
| 59 |
|
|
STP PSR_N | Set Negative flag [STP PSR_N]
|
| 60 |
|
|
STP PSR_I | Set Interrupt Enable flag [STP PSR_I]
|
| 61 |
|
|
STP PSR_GP4 | Set GP4 flag [STP PSR_GP4]
|
| 62 |
|
|
STP PSR_GP5 | Set GP5 flag [STP PSR_GP5]
|
| 63 |
|
|
STP PSR_GP6 | Set GP6 flag [STP PSR_GP6]
|
| 64 |
|
|
STP PSR_GP7 | Set GP7 flag [STP PSR_GP7]
|
| 65 |
|
|
BTT 0-7 | Test Bit # in R0. Set Zero flag or not.[BTT 2]
|
| 66 |
|
|
CLP PSR_Z | Clear Zero flag [CLP PSR_Z]
|
| 67 |
|
|
CLP PSR_C | Clear Carry flag [CLP PSR_C]
|
| 68 |
|
|
CLP PSR_N | Clear Negative flag [CLP PSR_N]
|
| 69 |
|
|
CLP PSR_I | Clear Interrupt Enable flag [CLP PSR_I]
|
| 70 |
|
|
CLP PSR_GP4 | Clear GP4 flag [CLP PSR_GP4]
|
| 71 |
|
|
CLP PSR_GP5 | Clear GP5 flag [CLP PSR_GP5]
|
| 72 |
|
|
CLP PSR_GP6 | Clear GP6 flag [CLP PSR_GP6]
|
| 73 |
|
|
CLP PSR_GP7 | Clear GP7 flag [CLP PSR_GP7]
|
| 74 |
|
|
T0X R0-R7 | R#=R0 [TX0 R2]
|
| 75 |
|
|
CMP R0-R7 | Compare R# With R0, put result in R0.[CMP R3]
|
| 76 |
|
|
PSH R0-R7 | Push R# onto the stack. [PSH R2]
|
| 77 |
|
|
POP R0-R7 | Pop R# from the stack. [POP R1]
|
| 78 |
|
|
DBNZ R0-R7 | Decrement register, and branch if result is zero
|
| 79 |
|
|
BNZ | Branch if Zero flag is not set. [BNZ LABEL]
|
| 80 |
|
|
BNC | Branch if Carry flag is not set. [BNC LABEL]
|
| 81 |
|
|
BNN | Branch if Negative flag is not set. [BNN LABEL]
|
| 82 |
|
|
BNI | Branch if Interrupt Enable flag is not set. [BNI LABEL]
|
| 83 |
|
|
BNGP4 | Branch If GP4 flag is not set. [BNGP4 LABEL]
|
| 84 |
|
|
BNGP5 | Branch If GP5 flag is not set. [BNGP5 LABEL]
|
| 85 |
|
|
BNGP6 | Branch If GP6 flag is not set. [BNGP6 LABEL]
|
| 86 |
|
|
BNGP7 | Branch If FP7 flag is not set. [BNGP7 LABEL]
|
| 87 |
|
|
BRZ | Branch on Zero flag is set. [BRZ LABEL]
|
| 88 |
|
|
BRC | Branch if Carry flag is set. [BRC LABEL]
|
| 89 |
|
|
BRN | Branch on Negative flag is set. [BRN LABEL]
|
| 90 |
|
|
BRI | Branch if Interrupt Enable flag is set. [BRI LABEL]
|
| 91 |
|
|
BRGP4 | Branch If GP4 flag is set. [BRGP4 LABEL]
|
| 92 |
|
|
BRGP5 | Branch If GP5 flag is set. [BRGP5 LABEL]
|
| 93 |
|
|
BRGP6 | Branch If GP6 flag is set. [BRGP6 LABEL]
|
| 94 |
|
|
BRGP7 | Branch If GP7 flag is set. [BRGP7 LABEL]
|
| 95 |
|
|
USR R0-R7 | User defined opcode. NOP if undefined. [USR R0]
|
| 96 |
|
|
INT 0-7 | (Call?) Interrupt number. [INT 7]
|
| 97 |
|
|
USR2 R0-R7 | User defined opcode 2. NOP if undefined. [USR2 R0]
|
| 98 |
|
|
RSP | Reset stack pointer. Uses R0+R1 for address. [RSP]
|
| 99 |
|
|
RTS | Return from subroutine. [RTS]
|
| 100 |
|
|
RTI | Return from interrupt. [RTI]
|
| 101 |
|
|
BRK | Break. For debugging. 5 clock NOP. [BRK]
|
| 102 |
|
|
JMP | Jump to absolute address. [JMP LABEL]
|
| 103 |
|
|
JSR | Jump to subroutine at absolute address. [JSR LABEL]
|
| 104 |
|
|
UPP R0-R7 | Increment R# and R#+1 as a 16-bit register [UPP R4]
|
| 105 |
|
|
STA R0-R7 | Store R# contents at Address [STA R0,$0020]
|
| 106 |
|
|
STX R0-R7 | Store R0 at location indexed by R# [STX R2]
|
| 107 |
|
|
STO R0-R7 | Store R0 at location indexed by R#+offset [STO R2,$aa]
|
| 108 |
|
|
LDI R0-R7 | Load an Integer into R# [LDI R2,#$00]
|
| 109 |
|
|
LDA R0-R7 | Load R# with the contents at address [LDA R4,$0366]
|
| 110 |
|
|
LDX R0-R7 | Load R0 with location indexed by R# [LDX R2]
|
| 111 |
|
|
LDO R0-R7 | Load R0 with location indexed by R#+offset [LDO R2,$ee]
|
