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1 178 jshamlet
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Open8 uRISC Assembly language description
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Hardware information
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The CPU has 8 8-bit general purpose registers available,
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R0-R7. In some operations, one register is paired with the
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next one so they behave like a 16-bit register.
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R0 is a special register, in that it is always the second
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unstated operand in commands that work with 2 values (ie.
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ADD R3 adds together R3 and R0), It also recieves the
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results of most commands that have results (ie. ADD R3
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stores the result of R0+R3 in R0).
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There are 4 normally used state flags. The Zero flag,
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the Carry flag, the Negative flag, and the Interrupt
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Enable flag. The Negative, Zero, and Carry flags are
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set/reset whenever any operation is carried out on ANY
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register. Ie. If you decrement R3 and it reaches zero,
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the Zero flag gets set. There are also 4 other General
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Purpose flags whose setting and checking is left up to
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you if you choose to use them.
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These flags are implemented in a bit of memory called
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the Program Status Register, or PSR.
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There's also a program counter, as you'd expect, but you
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can't access it's value from any of the opcodes, directly
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or otherwise. That fact, and the lack of a BRanch Always
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command, makes it tough to write easily relocateable
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code.
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OPCODE LISTING
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Opcode        Description [Example]
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------------------------------------------------------------------
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INC R0-07   | Increment Register [INC R4]
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ADC R0-07   | R0=R#+R0 using carry flag [ADC R4]
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TX0 R0-R7   | R0=R# [TX0 R2]
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OR  R0-R7   | R0=R0|R# [OR R6]
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AND R0-R7   | R0=R0&R# [AND R4]
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CLR R0      | Clears R0 [CLR R0]
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XOR R0-R7   | R0=R0^R# [XOR R2]
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ROL R0-R7   | R#=R#<<1. Roll R# Left [ROL R2]
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ROR R0-R7   | R#=R#>>1. Roll R# Right [ROR R2]
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DEC R0-R7   | R#=R#-1 [DEC R4]
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SBC R0-R7   | R0=R0-R# using carry flag [SBC R6]
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ADD R0-R7   | R0=R0+R# [ADD R3]
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MUL R0-R7   | R1:R0 = Rn * R0
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STP PSR_Z   | Set Zero flag [STP PSR_Z]
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STP PSR_C   | Set Carry flag [STP PSR_C]
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STP PSR_N   | Set Negative flag [STP PSR_N]
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STP PSR_I   | Set Interrupt Enable flag [STP PSR_I]
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STP PSR_GP4 | Set GP4 flag [STP PSR_GP4]
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STP PSR_GP5 | Set GP5 flag [STP PSR_GP5]
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STP PSR_GP6 | Set GP6 flag [STP PSR_GP6]
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STP PSR_GP7 | Set GP7 flag [STP PSR_GP7]
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BTT 0-7     | Test Bit # in R0. Set Zero flag or not.[BTT 2]
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CLP PSR_Z   | Clear Zero flag [CLP PSR_Z]
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CLP PSR_C   | Clear Carry flag [CLP PSR_C]
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CLP PSR_N   | Clear Negative flag [CLP PSR_N]
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CLP PSR_I   | Clear Interrupt Enable flag [CLP PSR_I]
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CLP PSR_GP4 | Clear GP4 flag [CLP PSR_GP4]
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CLP PSR_GP5 | Clear GP5 flag [CLP PSR_GP5]
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CLP PSR_GP6 | Clear GP6 flag [CLP PSR_GP6]
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CLP PSR_GP7 | Clear GP7 flag [CLP PSR_GP7]
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T0X R0-R7   | R#=R0 [TX0 R2]
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CMP R0-R7   | Compare R# With R0, put result in R0.[CMP R3]
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PSH R0-R7   | Push R# onto the stack. [PSH R2]
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POP R0-R7   | Pop R# from the stack. [POP R1]
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DBNZ R0-R7  | Decrement register, and branch if result is zero
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BNZ         | Branch if Zero flag is not set. [BNZ LABEL]
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BNC         | Branch if Carry flag is not set. [BNC LABEL]
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BNN         | Branch if Negative flag is not set. [BNN LABEL]
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BNI         | Branch if Interrupt Enable flag is not set. [BNI LABEL]
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BNGP4       | Branch If GP4 flag is not set. [BNGP4 LABEL]
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BNGP5       | Branch If GP5 flag is not set. [BNGP5 LABEL]
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BNGP6       | Branch If GP6 flag is not set. [BNGP6 LABEL]
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BNGP7       | Branch If FP7 flag is not set. [BNGP7 LABEL]
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BRZ         | Branch on Zero flag is set. [BRZ LABEL]
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BRC         | Branch if Carry flag is set. [BRC LABEL]
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BRN         | Branch on Negative flag is set. [BRN LABEL]
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BRI         | Branch if Interrupt Enable flag is set. [BRI LABEL]
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BRGP4       | Branch If GP4 flag is set. [BRGP4 LABEL]
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BRGP5       | Branch If GP5 flag is set. [BRGP5 LABEL]
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BRGP6       | Branch If GP6 flag is set. [BRGP6 LABEL]
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BRGP7       | Branch If GP7 flag is set. [BRGP7 LABEL]
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USR R0-R7   | User defined opcode. NOP if undefined. [USR R0]
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INT 0-7     | (Call?) Interrupt number. [INT 7]
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USR2 R0-R7  | User defined opcode 2. NOP if undefined. [USR2 R0]
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RSP         | Reset stack pointer. Uses R0+R1 for address. [RSP]
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RTS         | Return from subroutine. [RTS]
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RTI         | Return from interrupt. [RTI]
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BRK         | Break. For debugging. 5 clock NOP. [BRK]
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JMP         | Jump to absolute address. [JMP LABEL]
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JSR         | Jump to subroutine at absolute address. [JSR LABEL]
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UPP R0-R7   | Increment R# and R#+1 as a 16-bit register [UPP R4]
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STA R0-R7   | Store R# contents at Address [STA R0,$0020]
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STX R0-R7   | Store R0 at location indexed by R# [STX R2]
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STO R0-R7   | Store R0 at location indexed by R#+offset [STO R2,$aa]
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LDI R0-R7   | Load an Integer into R# [LDI R2,#$00]
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LDA R0-R7   | Load R# with the contents at address [LDA R4,$0366]
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LDX R0-R7   | Load R0 with location indexed by R# [LDX R2]
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LDO R0-R7   | Load R0 with location indexed by R#+offset [LDO R2,$ee]

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