Subversion Repositories open8_urisc

-- VHDL units : em_interface

-- Description: Connects all of the components that comprise the ROMEO/JAGM

--               ESAF test stimulus controller

--

-- Revision History

-- Author          Date     Change

------------------ -------- ---------------------------------------------------

-- Seth Henry      04/16/20 Version block added

library ieee;

  use ieee.std_logic_1164.all;

library work;

  use work.open8_pkg.all;

  use work.open8_cfg.all;

entity em_interface is

port(

  -- Master oscillator

  Ext_50M_Osc                : in  std_logic;

  -- Push buttons

  KEY0                       : in  std_logic;

  KEY1                       : in  std_logic;

  -- LED outputs

  LEDS                       : out std_logic_vector(7 downto 0);

  -- Configuration Switches

  DIPSW                      : in  std_logic_vector(3 downto 0);

  -- GPINs (input only)

  GPIN0                      : in  std_logic_vector(1 downto 0);

  GPIN1                      : in  std_logic_vector(1 downto 0);

  GPIN2                      : in  std_logic_vector(2 downto 0);

  -- GPIO

  GPIO0                      : inout std_logic_vector(33 downto 0);

  GPIO1                      : inout std_logic_vector(33 downto 0);

  GPIO2                      : inout std_logic_vector(12 downto 0)

);

end entity;

architecture behave of em_interface is

  -- I/O mapping aliases

  -- Clocks & Resets

  alias  Sys_Clock_50M       is Ext_50M_Osc;

  -- External Pushbuttons

  alias  FMSIM_PB_Reset      is GPIN2(0);

  alias  FPGA_PB_Reset       is GPIN2(2);

  alias  DBG_PB              is GPIO2(3);

  -- Diagnostic

  alias  JP1_1               is GPIN0(0);

  alias  JP1_3               is GPIN0(1);

  alias  JP1_37              is GPIO0(30);

  alias  JP1_38              is GPIO0(31);

  alias  JP1_39              is GPIO0(32);

  alias  JP1_40              is GPIO0(33);

  alias  JP2_4               is GPIO1(1);

  -- Status LED

  alias  Status_LED          is GPIO2(10);

  -- Telemetry Serial

  alias  TM_Tx_Out           is GPIO1(0);

  alias  TM_CTS_In           is GPIN1(1);

  -- Vector RX (TS Input)

  alias  Vec_Rx              is GPIN1(0);

  -- MAX 7221 SPI Interface

  alias  MX_LDCSn            is GPIO2(9);

  alias  Mx_Clock            is GPIO2(5);

  alias  Mx_Data             is GPIO2(7);

  -- SDLC Serial Interface

  alias  SDLC_EM2IF          is GPIO0(18);

  alias  SDLC_Clock          is GPIO0(19);

  alias  SDLC_IF2EM          is GPIO0(20);

  -- Relay/Discrete I/O

  alias  EM_Elec_Power       is GPIO2(8);

  alias  EM_Arm_Power        is GPIO0(29);

  alias  EM_Separation       is GPIO0(5);

  alias  EM_Detonate_Cmd_1   is GPIO0(17);

  alias  EM_Detonate_Cmd_2   is GPIO0(9);

  alias  EM_Test_G1          is GPIO0(7);

  alias  EM_Test_G2          is GPIO0(11);

  alias  EM_Test_Mode        is GPIO0(2);

  alias  EM_Config_ID_1      is GPIO0(0);

  alias  EM_Config_ID_2      is GPIO0(4);

  alias  EM_Config_ID_3      is GPIO0(8);

  alias  EM_Spare_1          is GPIO0(1);

  alias  EM_Int_Impact       is GPIO0(3);

  alias  EM_FPGA_POR_Reset   is GPIO0(6);

  alias  EM_PIC_POR_Reset    is GPIO0(10);

  alias  EM_Spare_Rly        is GPIO0(12);

  alias  EM_Accel_PDM        is GPIO2(11);

  -- Unused EM signals

  alias  EM_TXD_TST          is GPIO0(13);

  alias  EM_Aux_In_1         is GPIO0(14);

  alias  EM_Aux_Out_1        is GPIO0(15);

  alias  EM_RCV_TST          is GPIO0(16);

  -- PC FM Simulator IF          (NANO)

  alias  PC_Contact          is GPIO0(26);

  alias  PC_EM2FM            is GPIO0(27);

  alias  PC_FM2EM            is GPIO0(28);

  alias  PC_Fire_Out         is GPIO0(21);

  -- MC FM Simulator IF          (NANO)

  alias  MC_Contact          is GPIO0(23);

  alias  MC_EM2FM            is GPIO0(24);

  alias  MC_FM2EM            is GPIO0(25);

  alias  MC_Fire_Out         is GPIO0(22);

  -- NI DIO

  alias  NI_P0_0             is GPIO1(17);

  alias  NI_P0_1             is GPIO1(2);

  alias  NI_P0_2             is GPIO1(15);

  alias  NI_P0_3             is GPIO1(4);

  alias  NI_P0_4             is GPIO1(13);

  alias  NI_P0_5             is GPIO1(6);

  alias  NI_P0_6             is GPIO1(11);

  alias  NI_P0_7             is GPIO1(8);

  alias  NI_P1_0             is GPIO1(9);

  alias  NI_P1_1             is GPIO1(10);

  alias  NI_P1_2             is GPIO1(7);

  alias  NI_P1_3             is GPIO1(12);

  alias  NI_P1_4             is GPIO1(5);

  alias  NI_P1_5             is GPIO1(14);

  alias  NI_P1_6             is GPIO1(3);

  alias  NI_P1_7             is GPIO1(16);

  alias  NI_P2_0             is GPIO1(33);

  alias  NI_P2_1             is GPIO1(18);

  alias  NI_P2_2             is GPIO1(31);

  alias  NI_P2_3             is GPIO1(20);

  alias  NI_P2_4             is GPIO1(29);

  alias  NI_P2_5             is GPIO1(22);

  alias  NI_P2_6             is GPIO1(27);

  alias  NI_P2_7             is GPIO1(20);

  alias  NI_P3_0             is GPIO1(25);

  alias  NI_P3_1             is GPIO1(26);

  alias  NI_P3_2             is GPIO1(23);

  alias  NI_P3_3             is GPIO1(28);

  alias  NI_P3_4             is GPIO1(21);

  alias  NI_P3_5             is GPIO1(30);

  alias  NI_P3_6             is GPIO1(19);

  alias  NI_P3_7             is GPIO1(32);

  -- Internal mapping signals

  signal Sys_Async_Reset     : std_logic;

  signal Ext_Switches        : DATA_TYPE := x"00";

  signal CPU_Flags           : EXT_GP_FLAGS := "00000";

  signal BAR_LED             : DATA_TYPE := x"00";

  signal Vec_Req             : std_logic := '0';

  signal Vec_Index           : std_logic_vector(5 downto 0) := "000000";

  signal Vec_Data            : std_logic_vector(15 downto 0 ) := x"0000";

begin

  Reset_Input_proc: process( Sys_Clock_50M, FPGA_PB_Reset, NI_P0_7 )

  begin

    if( FPGA_PB_Reset = '0' or NI_P0_7 = '1' )then

      Sys_Async_Reset        <= '0';

    elsif( rising_edge( Sys_Clock_50M ) )then

      Sys_Async_Reset        <= '1';

    end if;

  end process;

  Vec_Req                    <= NI_P0_6;

  Vec_Index                  <= NI_P0_5 & NI_P0_4 & NI_P0_3 &

                                NI_P0_2 & NI_P0_1 & NI_P0_0;

  Vec_Data                   <= NI_P2_7 & NI_P2_6 & NI_P2_5 & NI_P2_4 &

                                NI_P2_3 & NI_P2_2 & NI_P2_1 & NI_P2_0 &

                                NI_P1_7 & NI_P1_6 & NI_P1_5 & NI_P1_4 &

                                NI_P1_3 & NI_P1_2 & NI_P1_1 & NI_P1_0;

  NI_P3_0                    <= BAR_LED(0);

  NI_P3_1                    <= BAR_LED(1);

  NI_P3_2                    <= BAR_LED(2);

  NI_P3_3                    <= BAR_LED(3);

  NI_P3_4                    <= BAR_LED(4);

  NI_P3_5                    <= BAR_LED(5);

  NI_P3_6                    <= BAR_LED(6);

  NI_P3_7                    <= BAR_LED(7);

  LEDS                       <= BAR_LED;

  Ext_Switches               <= DIPSW & KEY1 & KEY0 & DBG_PB & FMSIM_PB_Reset;

  JP1_37                     <= CPU_Flags(EXT_ISR);

  JP1_38                     <= CPU_Flags(EXT_GP5);

  JP1_39                     <= CPU_Flags(EXT_GP6);

  JP1_40                     <= CPU_Flags(EXT_GP7);

  U_CORE : entity work.em_core

  port map(

    Sys_Async_Reset          => Sys_Async_Reset,

    Sys_Clock_50M            => Sys_Clock_50M,

    -- Switches

    Ext_Switches             => Ext_Switches,

    -- LEDS

    BAR_LED                  => BAR_LED,

    Status_LED               => Status_LED,

    -- CPU Flags

    CPU_Flags                => CPU_Flags,

    -- Telemetry Serial

    TM_Tx_Out                => TM_Tx_Out,

    TM_CTS_In                => TM_CTS_In,

    -- MAX 7221 SPI Interface

    MX_LDCSn                 => MX_LDCSn,

    Mx_Clock                 => Mx_Clock,

    Mx_Data                  => Mx_Data,

    -- Vector RX (Aux TS Input)

    Vec_Req                  => Vec_Req,

    Vec_Index                => Vec_Index,

    Vec_Data                 => Vec_Data,

    Vec_Rx                   => Vec_Rx,

    -- SDLC Serial Interface

    SDLC_EM2IF               => SDLC_EM2IF,

    SDLC_Clock               => SDLC_Clock,

    SDLC_IF2EM               => SDLC_IF2EM,

    -- Relay/Discrete I/O

    EM_Elec_Power            => EM_Elec_Power,

    EM_Arm_Power             => EM_Arm_Power,

    EM_Separation            => EM_Separation,

    EM_Detonate_Cmd_1        => EM_Detonate_Cmd_1,

    EM_Detonate_Cmd_2        => EM_Detonate_Cmd_2,

    EM_Test_G1               => EM_Test_G1,

    EM_Test_G2               => EM_Test_G2,

    EM_Test_Mode             => EM_Test_Mode,

    EM_Config_ID_1           => EM_Config_ID_1,

    EM_Config_ID_2           => EM_Config_ID_2,

    EM_Config_ID_3           => EM_Config_ID_3,

    EM_Spare_1               => EM_Spare_1,

    EM_Int_Impact            => EM_Int_Impact,

    EM_FPGA_POR_Reset        => EM_FPGA_POR_Reset,

    EM_PIC_POR_Reset         => EM_PIC_POR_Reset,

    EM_Spare_Rly             => EM_Spare_Rly,

    EM_Accel_PDM             => EM_Accel_PDM,

    -- PC FM Simulator IF

    PC_Contact               => PC_Contact,

    PC_EM2FM                 => PC_EM2FM,

    PC_FM2EM                 => PC_FM2EM,

    PC_Fire_Out              => PC_Fire_Out,

    -- MC FM Simulator IF

    MC_Contact               => MC_Contact,

    MC_EM2FM                 => MC_EM2FM,

    MC_FM2EM                 => MC_FM2EM,

    MC_Fire_Out              => MC_Fire_Out

  );

end architecture;