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-- VHDL Units : Open8_cfg
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-- Description: Contains the common project specific constants to configure
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-- an Open8 system for the ROMEO ESAF test set
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--
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-- Revision History
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/16/20 Design Start
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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library work;
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use work.open8_pkg.all;
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package open8_cfg is
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-- Internal Clock Frequency
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constant Clock_Frequency : real := 120000000.0;
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-- Open8 CPU Options
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constant Allow_Stack_Address_Move : boolean := TRUE;
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constant Stack_Xfer_Flag : integer := PSR_GP4;
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constant Enable_Auto_Increment : boolean := TRUE;
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constant BRK_Implements_WAI : boolean := TRUE;
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constant Enable_NMI : boolean := TRUE;
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constant Sequential_Interrupts : boolean := TRUE;
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constant RTI_Ignores_GP_Flags : boolean := TRUE;
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constant Supervisor_Mode : boolean := TRUE;
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constant Unsigned_Index_Offsets : boolean := TRUE;
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constant Default_Int_Mask : DATA_TYPE := x"00";
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-- System Memory Map
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constant RAM_Address : ADDRESS_TYPE := x"0000"; -- System RAM
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constant WPR_Address : ADDRESS_TYPE := x"1000"; -- Write Protect Mask
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constant WQL_Address : ADDRESS_TYPE := x"1100"; -- Write Qual Register
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constant INT_Address : ADDRESS_TYPE := x"1200"; -- Interrupt Manager
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constant ROM_Address : ADDRESS_TYPE := x"8000"; -- Application ROM
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constant ISR_Start_Addr : ADDRESS_TYPE := x"FFF0"; -- ISR vector table
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-- RAM size is used to calculate the initial stack pointer, which is set at
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-- the top of the RAM region.
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constant RAM_Size : integer := 4096;
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constant RAM_Write_Protect : boolean := TRUE;
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-- CPU Interrupt assignments - Note that interrupt 0 is the NMI (non-maskable)
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-- also, because these are handled by the CPU, they are in priority order
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-- from 0 (highest) to 7 (lowest).
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constant CPU_INT_RAM : integer range 0 to OPEN8_DATA_WIDTH - 1 := 0;
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constant CPU_INT_PIT : integer range 0 to OPEN8_DATA_WIDTH - 1 := 1;
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constant CPU_INT_EXT : integer range 0 to OPEN8_DATA_WIDTH - 1 := 2;
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-- I/O Interrupt assignments (Not technically required, as software will overwrite
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-- this during initialization)
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constant Default_IO_Int_Mask : ADDRESS_TYPE := x"0000";
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-- Set this to the number of readable modules in the design, as it sets the
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-- number of ports on the read aggregator function.
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constant NUM_READ_BUSES : integer := 4;
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-- Read Data Bus aggregator and bus assignments.
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-- Note that the ordering isn't important, only that each device has a
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-- unique number less than NUM_READ_BUSES.
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constant RDB_RAM : integer range 0 to NUM_READ_BUSES - 1 := 0;
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constant RDB_WQL : integer range 0 to NUM_READ_BUSES - 1 := 1;
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constant RDB_INT : integer range 0 to NUM_READ_BUSES - 1 := 2;
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constant RDB_ROM : integer range 0 to NUM_READ_BUSES - 1 := 3;
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-- System configuration calculations - no adjustable parameters below this point
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type OPEN8_BUS_ARRAY is array(0 to NUM_READ_BUSES - 1) of DATA_TYPE;
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constant INIT_READ_BUS : OPEN8_BUS_ARRAY := (others => OPEN8_NULLBUS);
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function merge_buses (x : in OPEN8_BUS_ARRAY) return DATA_TYPE;
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-- Compute the stack start address based on the RAM size
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constant RAM_Vector_Size : integer := ceil_log2(RAM_Size - 1);
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constant RAM_End_Addr : std_logic_vector(RAM_Vector_Size - 1 downto 0)
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:= (others => '1');
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constant Stack_Start_Addr : ADDRESS_TYPE := RAM_Address + RAM_End_Addr;
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end package;
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package body open8_cfg is
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function merge_buses (x : in OPEN8_BUS_ARRAY) return DATA_TYPE is
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variable i : integer := 0;
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variable retval : DATA_TYPE := x"00";
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begin
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retval := x"00";
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for i in 0 to NUM_READ_BUSES - 1 loop
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retval := retval or x(i);
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end loop;
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return retval;
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end function;
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end package body;
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