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[/] [open8_urisc/] [trunk/] [VHDL/] [Open8_pkg.vhd] - Blame information for rev 142

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1 7 jshamlet
-- Copyright (c)2006, Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- VHDL Units :  Open8_pkg
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-- Description:  Contains constant definitions for the Open8 processor
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      07/22/06 Design Start
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library ieee;
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use ieee.std_logic_1164.all;
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package Open8_pkg is
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  -- These subtypes can be used with external peripherals to simplify
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  --  connection to the core. 
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  subtype ADDRESS_TYPE is std_logic_vector(15 downto 0);
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  subtype DATA_TYPE    is std_logic_vector(7 downto 0);
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  -- Note: INTERRUPT_BUNDLE must be exactly the same width as DATA_TYPE
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  subtype INTERRUPT_BUNDLE is DATA_TYPE;
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  -- Component declaration
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  component Open8_CPU is
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  generic(
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    Stack_Start_Addr         : ADDRESS_TYPE;
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    Allow_Stack_Address_Move : std_logic := '0';
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    ISR_Start_Addr           : ADDRESS_TYPE;
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    Program_Start_Addr       : ADDRESS_TYPE;
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    Default_Interrupt_Mask   : DATA_TYPE;
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    Enable_CPU_Halt          : std_logic := '0';
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    Enable_Auto_Increment    : std_logic := '0' );
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  port(
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    Clock                    : in  std_logic;
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    Reset_n                  : in  std_logic;
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    CPU_Halt                 : in  std_logic;
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    Interrupts               : in  INTERRUPT_BUNDLE;
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    Address                  : out ADDRESS_TYPE;
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    Rd_Data                  : in  DATA_TYPE;
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    Rd_Enable                : out std_logic;
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    Wr_Data                  : out DATA_TYPE;
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    Wr_Enable                : out std_logic );
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  end component;
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end Open8_pkg;
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package body Open8_pkg is
68 10 khays
end package body;

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