OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [Open8_pkg.vhd] - Blame information for rev 188

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 185 jshamlet
-- Copyright (c)2006,2011,2012,2013,2015,2020 Jeremy Seth Henry
2 181 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
22
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
 
24
-- VHDL Units :  Open8_pkg
25
-- Description:  Contains constant definitions for the Open8 processor
26
-- Revision History
27
-- Author          Date     Change
28
------------------ -------- ---------------------------------------------------
29
-- Seth Henry      07/22/06 Design Start
30
-- Seth Henry      02/03/12 Updated generics to match current model
31
-- Seth Henry      10/29/15 Migrated type/constant definitions to this file
32 185 jshamlet
-- Seth Henry      03/09/20 Created new ALU/SP opcodes for handling new RSP
33
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
34
--                           the assembler names. Also removed superfluous
35
--                           signals in the ALU and PC records.
36 188 jshamlet
-- Seth Henry      03/17/20 Added new subtype and constants for external
37
--                           GP flags.
38 181 jshamlet
 
39
library ieee;
40
use ieee.std_logic_1164.all;
41 185 jshamlet
use ieee.std_logic_arith.all;
42 181 jshamlet
 
43
package Open8_pkg is
44
 
45
-------------------------------------------------------------------------------
46
-- External constants and type declarations
47
--
48
-- These subtypes can be used with external peripherals to simplify
49
--  connection to the core.
50
-------------------------------------------------------------------------------
51
 
52
  -- These must never be changed, as the core requires them to be these static
53
  --  values for proper operation. These are ONLY defined here to allow user
54 185 jshamlet
  --  code to dynamically configure itself to match the Open8 core.
55 181 jshamlet
 
56
  constant OPEN8_ADDR_WIDTH  : integer := 16; -- DON'T EVEN CONTEMPLATE
57
  constant OPEN8_DATA_WIDTH  : integer := 8;  -- CHANGING THESE!
58
 
59
  subtype ADDRESS_TYPE is std_logic_vector(OPEN8_ADDR_WIDTH - 1 downto 0);
60
  subtype DATA_TYPE    is std_logic_vector(OPEN8_DATA_WIDTH - 1 downto 0);
61
  -- Note: INTERRUPT_BUNDLE must be exactly the same width as DATA_TYPE
62
  subtype INTERRUPT_BUNDLE is DATA_TYPE;
63
 
64 188 jshamlet
  subtype EXT_GP_FLAGS is std_logic_vector(3 downto 0);
65
 
66
  constant EXT_GP4           : integer := 0;
67
  constant EXT_GP5           : integer := 1;
68
  constant EXT_GP6           : integer := 2;
69
  constant EXT_GP7           : integer := 3;
70
 
71 181 jshamlet
  -- Component declaration
72 185 jshamlet
  --  (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
73 183 jshamlet
  component o8_cpu is
74 181 jshamlet
  generic(
75 185 jshamlet
    Program_Start_Addr       : ADDRESS_TYPE := x"8000";
76
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0";
77
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF";
78
    Allow_Stack_Address_Move : boolean      := false;
79
    Stack_Xfer_Flag          : integer      := 4;
80
    Enable_Auto_Increment    : boolean      := false;
81
    BRK_Implements_WAI       : boolean      := false;
82
    Enable_NMI               : boolean      := true;
83 188 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;
84 185 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";
85
    Reset_Level              : std_logic    := '0' );
86 181 jshamlet
  port(
87
    Clock                    : in  std_logic;
88
    Reset                    : in  std_logic;
89 187 jshamlet
    CPU_Halt                 : in  std_logic;
90 181 jshamlet
    Interrupts               : in  INTERRUPT_BUNDLE;
91 188 jshamlet
    GP_Flags                 : out EXT_GP_FLAGS;
92 181 jshamlet
    Address                  : out ADDRESS_TYPE;
93
    Rd_Data                  : in  DATA_TYPE;
94
    Rd_Enable                : out std_logic;
95
    Wr_Data                  : out DATA_TYPE;
96
    Wr_Enable                : out std_logic );
97
  end component;
98
 
99
-------------------------------------------------------------------------------
100
-- Internal constants and type declarations.
101
--
102
-- These are only used in the actual model, and aren't generally useful for
103
--  external application.
104
-------------------------------------------------------------------------------
105
 
106
  subtype OPCODE_TYPE  is std_logic_vector(4 downto 0);
107
  subtype SUBOP_TYPE   is std_logic_vector(2 downto 0);
108
 
109
  -- All opcodes should be identical to the opcode used by the assembler
110
  -- In this case, they match the original V8/ARC uRISC ISA
111
  constant OP_INC            : OPCODE_TYPE := "00000";
112
  constant OP_ADC            : OPCODE_TYPE := "00001";
113
  constant OP_TX0            : OPCODE_TYPE := "00010";
114
  constant OP_OR             : OPCODE_TYPE := "00011";
115
  constant OP_AND            : OPCODE_TYPE := "00100";
116
  constant OP_XOR            : OPCODE_TYPE := "00101";
117
  constant OP_ROL            : OPCODE_TYPE := "00110";
118
  constant OP_ROR            : OPCODE_TYPE := "00111";
119
  constant OP_DEC            : OPCODE_TYPE := "01000";
120
  constant OP_SBC            : OPCODE_TYPE := "01001";
121
  constant OP_ADD            : OPCODE_TYPE := "01010";
122
  constant OP_STP            : OPCODE_TYPE := "01011";
123
  constant OP_BTT            : OPCODE_TYPE := "01100";
124
  constant OP_CLP            : OPCODE_TYPE := "01101";
125
  constant OP_T0X            : OPCODE_TYPE := "01110";
126
  constant OP_CMP            : OPCODE_TYPE := "01111";
127
  constant OP_PSH            : OPCODE_TYPE := "10000";
128
  constant OP_POP            : OPCODE_TYPE := "10001";
129
  constant OP_BR0            : OPCODE_TYPE := "10010";
130
  constant OP_BR1            : OPCODE_TYPE := "10011";
131
  constant OP_DBNZ           : OPCODE_TYPE := "10100"; -- USR
132
  constant OP_INT            : OPCODE_TYPE := "10101";
133
  constant OP_MUL            : OPCODE_TYPE := "10110"; -- USR2
134
  constant OP_STK            : OPCODE_TYPE := "10111";
135
  constant OP_UPP            : OPCODE_TYPE := "11000";
136
  constant OP_STA            : OPCODE_TYPE := "11001";
137
  constant OP_STX            : OPCODE_TYPE := "11010";
138
  constant OP_STO            : OPCODE_TYPE := "11011";
139
  constant OP_LDI            : OPCODE_TYPE := "11100";
140
  constant OP_LDA            : OPCODE_TYPE := "11101";
141
  constant OP_LDX            : OPCODE_TYPE := "11110";
142
  constant OP_LDO            : OPCODE_TYPE := "11111";
143
 
144
  -- OP_STK uses the lower 3 bits to further refine the instruction by
145 186 jshamlet
  --  repurposing the source register field. These "sub opcodes" take
146
  --  the place of the register select for the OP_STK opcode
147 181 jshamlet
  constant SOP_RSP           : SUBOP_TYPE := "000";
148
  constant SOP_RTS           : SUBOP_TYPE := "001";
149
  constant SOP_RTI           : SUBOP_TYPE := "010";
150
  constant SOP_BRK           : SUBOP_TYPE := "011";
151
  constant SOP_JMP           : SUBOP_TYPE := "100";
152
  constant SOP_SMSK          : SUBOP_TYPE := "101";
153
  constant SOP_GMSK          : SUBOP_TYPE := "110";
154
  constant SOP_JSR           : SUBOP_TYPE := "111";
155
 
156
  type CPU_STATES is (
157
      -- Instruction fetch & Decode
158 187 jshamlet
    IPF_C0, IPF_C1, IPF_C2, IDC_C0,
159 181 jshamlet
    -- Branching
160
    BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
161
    -- Loads
162 185 jshamlet
    LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1,
163
    LDO_C1, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
164 181 jshamlet
    -- Stores
165
    STA_C1, STA_C2, STA_C3, STO_C1, STO_C2, STX_C1, STX_C2,
166
    -- 2-cycle math
167
    MUL_C1, UPP_C1,
168
    -- Stack
169
    PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
170
    -- Subroutines & Interrupts
171 187 jshamlet
    WAI_Cx, WAH_Cx, BRK_C1,
172 186 jshamlet
    ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
173 187 jshamlet
    RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6
174
     );
175 181 jshamlet
 
176
  type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
177
                       CACHE_PREFETCH );
178
 
179 185 jshamlet
  type PC_MODES is ( PC_INCR, PC_LOAD );
180 181 jshamlet
 
181
  type PC_CTRL_TYPE is record
182
    Oper                     : PC_MODES;
183
    Offset                   : DATA_TYPE;
184
  end record;
185
 
186 185 jshamlet
  -- These are fixed constant offsets to the program counter logic, which is
187
  --  always either incrementing or loading.
188
  constant PC_NEXT           : DATA_TYPE := x"03";
189
  constant PC_IDLE           : DATA_TYPE := x"02";
190
  constant PC_REV1           : DATA_TYPE := x"01";
191
  constant PC_REV2           : DATA_TYPE := x"00";
192
  constant PC_REV3           : DATA_TYPE := x"FF";
193
 
194 181 jshamlet
  type SP_MODES is ( SP_IDLE, SP_CLR, SP_SET, SP_POP, SP_PUSH );
195
 
196
  type SP_CTRL_TYPE is record
197
    Oper                     : SP_MODES;
198
  end record;
199
 
200
  type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
201
                     DATA_WR_REG, DATA_WR_FLAG, DATA_WR_PC );
202
 
203
  type DATA_CTRL_TYPE is record
204
    Src                      : DP_MODES;
205
    Reg                      : SUBOP_TYPE;
206
  end record;
207
 
208 182 jshamlet
  constant PC_LSB            : SUBOP_TYPE := "000";
209
  constant PC_MSB            : SUBOP_TYPE := "001";
210
 
211 181 jshamlet
  type INT_CTRL_TYPE is record
212
    Mask_Set                 : std_logic;
213
    Soft_Ints                : INTERRUPT_BUNDLE;
214
    Incr_ISR                 : std_logic;
215
  end record;
216
 
217 185 jshamlet
  -- Most of the ALU instructions are the same as their Opcode equivalents,
218
  --  with exceptions for IDLE, UPP2, RFLG, RSP, and GMSK, which perform
219
  --  internal operations not otherwise exposed by the instruction set.
220 181 jshamlet
  constant ALU_INC           : OPCODE_TYPE := "00000"; -- x"00"
221
  constant ALU_ADC           : OPCODE_TYPE := "00001"; -- x"01"
222
  constant ALU_TX0           : OPCODE_TYPE := "00010"; -- x"02"
223
  constant ALU_OR            : OPCODE_TYPE := "00011"; -- x"03"
224
  constant ALU_AND           : OPCODE_TYPE := "00100"; -- x"04"
225
  constant ALU_XOR           : OPCODE_TYPE := "00101"; -- x"05"
226
  constant ALU_ROL           : OPCODE_TYPE := "00110"; -- x"06"
227
  constant ALU_ROR           : OPCODE_TYPE := "00111"; -- x"07"
228
  constant ALU_DEC           : OPCODE_TYPE := "01000"; -- x"08"
229
  constant ALU_SBC           : OPCODE_TYPE := "01001"; -- x"09"
230
  constant ALU_ADD           : OPCODE_TYPE := "01010"; -- x"0A"
231
  constant ALU_STP           : OPCODE_TYPE := "01011"; -- x"0B"
232
  constant ALU_BTT           : OPCODE_TYPE := "01100"; -- x"0C"
233
  constant ALU_CLP           : OPCODE_TYPE := "01101"; -- x"0D"
234
  constant ALU_T0X           : OPCODE_TYPE := "01110"; -- x"0E"
235
  constant ALU_CMP           : OPCODE_TYPE := "01111"; -- x"0F"
236
  constant ALU_POP           : OPCODE_TYPE := "10001"; -- x"11"
237
  constant ALU_MUL           : OPCODE_TYPE := "10110"; -- x"16"
238
  constant ALU_UPP           : OPCODE_TYPE := "11000"; -- x"18"
239
  constant ALU_LDI           : OPCODE_TYPE := "11100"; -- x"1C"
240
 
241
  constant ALU_IDLE          : OPCODE_TYPE := "10000"; -- x"10"
242
  constant ALU_UPP2          : OPCODE_TYPE := "10010"; -- x"12"
243
  constant ALU_RFLG          : OPCODE_TYPE := "10011"; -- x"13"
244 185 jshamlet
  constant ALU_RSP           : OPCODE_TYPE := "10111"; -- x"17"
245
  constant ALU_GMSK          : OPCODE_TYPE := "11111"; -- x"1F"
246 181 jshamlet
 
247 185 jshamlet
  -- These should match the assembler's definitions for the flags
248
  constant PSR_Z             : integer := 0;
249
  constant PSR_C             : integer := 1;
250
  constant PSR_N             : integer := 2;
251
  constant PSR_I             : integer := 3;
252
  constant PSR_GP4           : integer := 4;
253 186 jshamlet
  constant PSR_GP5           : integer := 5;
254
  constant PSR_GP6           : integer := 6;
255
  constant PSR_GP7           : integer := 7;
256
 
257
  type ALU_CTRL_TYPE is record
258
    Oper                     : OPCODE_TYPE;
259
    Reg                      : SUBOP_TYPE;
260
  end record;
261
 
262
  constant ACCUM             : SUBOP_TYPE := "000";
263
 
264
  type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
265
 
266
  subtype FLAG_TYPE is DATA_TYPE;
267
 
268
end Open8_pkg;
269
 
270
package body Open8_pkg is
271
end package body;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.