OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [Open8_pkg.vhd] - Blame information for rev 253

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 185 jshamlet
-- Copyright (c)2006,2011,2012,2013,2015,2020 Jeremy Seth Henry
2 181 jshamlet
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 220 jshamlet
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 181 jshamlet
 
24
-- VHDL Units :  Open8_pkg
25
-- Description:  Contains constant definitions for the Open8 processor
26 220 jshamlet
--
27 181 jshamlet
-- Revision History
28
-- Author          Date     Change
29
------------------ -------- ---------------------------------------------------
30
-- Seth Henry      07/22/06 Design Start
31
-- Seth Henry      02/03/12 Updated generics to match current model
32
-- Seth Henry      10/29/15 Migrated type/constant definitions to this file
33 227 jshamlet
-- Seth Henry      03/09/20 Created new ALU/SP opcodes for handling new RSP
34 185 jshamlet
-- Seth Henry      03/12/20 Rationalized the naming of the CPU flags to match
35
--                           the assembler names. Also removed superfluous
36
--                           signals in the ALU and PC records.
37 188 jshamlet
-- Seth Henry      03/17/20 Added new subtype and constants for external
38
--                           GP flags.
39 189 jshamlet
-- Seth Henry      03/18/20 Added the ceil_log2 function, since it is used in
40
--                           memory sizing calculations.
41 210 jshamlet
-- Seth Henry      04/09/20 Added the I bit to the exported flags for use in
42
--                           memory protection schemes.
43 226 jshamlet
-- Seth Henry      04/16/20 Added the OPEN8_BUS_TYPE record to simplify
44
--                           peripheral connections.
45 181 jshamlet
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48 185 jshamlet
use ieee.std_logic_arith.all;
49 181 jshamlet
 
50
package Open8_pkg is
51
 
52
-------------------------------------------------------------------------------
53
-- External constants and type declarations
54
--
55
-- These subtypes can be used with external peripherals to simplify
56
--  connection to the core.
57
-------------------------------------------------------------------------------
58
 
59
  -- These must never be changed, as the core requires them to be these static
60
  --  values for proper operation. These are ONLY defined here to allow user
61 185 jshamlet
  --  code to dynamically configure itself to match the Open8 core.
62 181 jshamlet
 
63
  constant OPEN8_ADDR_WIDTH  : integer := 16; -- DON'T EVEN CONTEMPLATE
64
  constant OPEN8_DATA_WIDTH  : integer := 8;  -- CHANGING THESE!
65
 
66
  subtype ADDRESS_TYPE is std_logic_vector(OPEN8_ADDR_WIDTH - 1 downto 0);
67
  subtype DATA_TYPE    is std_logic_vector(OPEN8_DATA_WIDTH - 1 downto 0);
68
  -- Note: INTERRUPT_BUNDLE must be exactly the same width as DATA_TYPE
69
  subtype INTERRUPT_BUNDLE is DATA_TYPE;
70
 
71 210 jshamlet
  subtype EXT_GP_FLAGS is std_logic_vector(4 downto 0);
72 188 jshamlet
 
73 210 jshamlet
  constant EXT_ISR           : integer := 0;
74
  constant EXT_GP4           : integer := 1;
75
  constant EXT_GP5           : integer := 2;
76
  constant EXT_GP6           : integer := 3;
77
  constant EXT_GP7           : integer := 4;
78 188 jshamlet
 
79 191 jshamlet
  constant OPEN8_NULLBUS     : DATA_TYPE := x"00";
80
 
81 228 jshamlet
  constant Reset_Level       : std_logic := '1';
82
 
83 223 jshamlet
  type OPEN8_BUS_TYPE is record
84 224 jshamlet
    Clock                    : std_logic;
85
    Reset                    : std_logic;
86
    uSec_Tick                : std_logic;
87 223 jshamlet
    Address                  : ADDRESS_TYPE;
88
    Wr_En                    : std_logic;
89
    Wr_Data                  : DATA_TYPE;
90
    Rd_En                    : std_logic;
91 224 jshamlet
    GP_Flags                 : EXT_GP_FLAGS;
92 223 jshamlet
  end record;
93
 
94 228 jshamlet
  constant INIT_OPEN8_BUS    : OPEN8_BUS_TYPE := (
95
                                 '0',           -- Clock
96
                                 Reset_Level,   -- Reset
97
                                 '0',           -- uSec_Tick
98
                                 x"0000",       -- Address
99
                                 '0',           -- Wr_En
100
                                 OPEN8_NULLBUS, -- Wr_Data
101
                                 '0',           -- Rd_En
102
                                 "00000"        -- GP_Flags
103
                               );
104 224 jshamlet
 
105 181 jshamlet
  -- Component declaration
106 185 jshamlet
  --  (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
107 183 jshamlet
  component o8_cpu is
108 181 jshamlet
  generic(
109 185 jshamlet
    Program_Start_Addr       : ADDRESS_TYPE := x"8000";
110
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0";
111
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF";
112
    Allow_Stack_Address_Move : boolean      := false;
113
    Stack_Xfer_Flag          : integer      := 4;
114
    Enable_Auto_Increment    : boolean      := false;
115
    BRK_Implements_WAI       : boolean      := false;
116
    Enable_NMI               : boolean      := true;
117 188 jshamlet
    RTI_Ignores_GP_Flags     : boolean      := false;
118 185 jshamlet
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";
119 224 jshamlet
    Clock_Frequency          : real
120
  );
121 181 jshamlet
  port(
122
    Clock                    : in  std_logic;
123 224 jshamlet
    PLL_Locked               : in  std_logic;
124 226 jshamlet
    Halt_Req                 : in  std_logic := '0';
125
    Halt_Ack                 : out std_logic;
126 223 jshamlet
    Open8_Bus                : out OPEN8_BUS_TYPE;
127 181 jshamlet
    Rd_Data                  : in  DATA_TYPE;
128 224 jshamlet
    Interrupts               : in  INTERRUPT_BUNDLE := x"00"
129 223 jshamlet
  );
130 181 jshamlet
  end component;
131
 
132 189 jshamlet
  -- This function is used to calculate RAM parameters, but is generally
133
  --  useful for making things more generic.
134
  function ceil_log2 (x : in natural) return natural;
135
 
136 181 jshamlet
-------------------------------------------------------------------------------
137
-- Internal constants and type declarations.
138
--
139
-- These are only used in the actual model, and aren't generally useful for
140
--  external application.
141
-------------------------------------------------------------------------------
142
 
143
  subtype OPCODE_TYPE  is std_logic_vector(4 downto 0);
144
  subtype SUBOP_TYPE   is std_logic_vector(2 downto 0);
145
 
146
  -- All opcodes should be identical to the opcode used by the assembler
147
  -- In this case, they match the original V8/ARC uRISC ISA
148
  constant OP_INC            : OPCODE_TYPE := "00000";
149
  constant OP_ADC            : OPCODE_TYPE := "00001";
150
  constant OP_TX0            : OPCODE_TYPE := "00010";
151
  constant OP_OR             : OPCODE_TYPE := "00011";
152
  constant OP_AND            : OPCODE_TYPE := "00100";
153
  constant OP_XOR            : OPCODE_TYPE := "00101";
154
  constant OP_ROL            : OPCODE_TYPE := "00110";
155
  constant OP_ROR            : OPCODE_TYPE := "00111";
156
  constant OP_DEC            : OPCODE_TYPE := "01000";
157
  constant OP_SBC            : OPCODE_TYPE := "01001";
158
  constant OP_ADD            : OPCODE_TYPE := "01010";
159
  constant OP_STP            : OPCODE_TYPE := "01011";
160
  constant OP_BTT            : OPCODE_TYPE := "01100";
161
  constant OP_CLP            : OPCODE_TYPE := "01101";
162
  constant OP_T0X            : OPCODE_TYPE := "01110";
163
  constant OP_CMP            : OPCODE_TYPE := "01111";
164
  constant OP_PSH            : OPCODE_TYPE := "10000";
165
  constant OP_POP            : OPCODE_TYPE := "10001";
166
  constant OP_BR0            : OPCODE_TYPE := "10010";
167
  constant OP_BR1            : OPCODE_TYPE := "10011";
168
  constant OP_DBNZ           : OPCODE_TYPE := "10100"; -- USR
169
  constant OP_INT            : OPCODE_TYPE := "10101";
170
  constant OP_MUL            : OPCODE_TYPE := "10110"; -- USR2
171
  constant OP_STK            : OPCODE_TYPE := "10111";
172
  constant OP_UPP            : OPCODE_TYPE := "11000";
173
  constant OP_STA            : OPCODE_TYPE := "11001";
174
  constant OP_STX            : OPCODE_TYPE := "11010";
175
  constant OP_STO            : OPCODE_TYPE := "11011";
176
  constant OP_LDI            : OPCODE_TYPE := "11100";
177
  constant OP_LDA            : OPCODE_TYPE := "11101";
178
  constant OP_LDX            : OPCODE_TYPE := "11110";
179
  constant OP_LDO            : OPCODE_TYPE := "11111";
180
 
181
  -- OP_STK uses the lower 3 bits to further refine the instruction by
182 186 jshamlet
  --  repurposing the source register field. These "sub opcodes" take
183
  --  the place of the register select for the OP_STK opcode
184 181 jshamlet
  constant SOP_RSP           : SUBOP_TYPE := "000";
185
  constant SOP_RTS           : SUBOP_TYPE := "001";
186
  constant SOP_RTI           : SUBOP_TYPE := "010";
187
  constant SOP_BRK           : SUBOP_TYPE := "011";
188
  constant SOP_JMP           : SUBOP_TYPE := "100";
189
  constant SOP_SMSK          : SUBOP_TYPE := "101";
190
  constant SOP_GMSK          : SUBOP_TYPE := "110";
191
  constant SOP_JSR           : SUBOP_TYPE := "111";
192
 
193
  type CPU_STATES is (
194
      -- Instruction fetch & Decode
195 187 jshamlet
    IPF_C0, IPF_C1, IPF_C2, IDC_C0,
196 181 jshamlet
    -- Branching
197
    BRN_C1, DBNZ_C1, JMP_C1, JMP_C2,
198
    -- Loads
199 185 jshamlet
    LDA_C1, LDA_C2, LDA_C3, LDA_C4, LDI_C1,
200 251 jshamlet
    LDO_C1, LDO_C2, LDX_C1, LDX_C2, LDX_C3, LDX_C4,
201 181 jshamlet
    -- Stores
202 251 jshamlet
    STA_C1, STA_C2, STA_C3, STO_C1, STO_C2, STO_C3, STX_C1, STX_C2,
203 181 jshamlet
    -- 2-cycle math
204
    MUL_C1, UPP_C1,
205
    -- Stack
206
    PSH_C1, POP_C1, POP_C2, POP_C3, POP_C4,
207
    -- Subroutines & Interrupts
208 187 jshamlet
    WAI_Cx, WAH_Cx, BRK_C1,
209 186 jshamlet
    ISR_C1, ISR_C2, ISR_C3, JSR_C1, JSR_C2,
210 187 jshamlet
    RTS_C1, RTS_C2, RTS_C3, RTS_C4, RTS_C5, RTI_C6
211
     );
212 181 jshamlet
 
213
  type CACHE_MODES is (CACHE_IDLE, CACHE_INSTR, CACHE_OPER1, CACHE_OPER2,
214
                       CACHE_PREFETCH );
215
 
216 185 jshamlet
  type PC_MODES is ( PC_INCR, PC_LOAD );
217 181 jshamlet
 
218
  type PC_CTRL_TYPE is record
219
    Oper                     : PC_MODES;
220
    Offset                   : DATA_TYPE;
221
  end record;
222
 
223 185 jshamlet
  -- These are fixed constant offsets to the program counter logic, which is
224
  --  always either incrementing or loading.
225
  constant PC_NEXT           : DATA_TYPE := x"03";
226
  constant PC_IDLE           : DATA_TYPE := x"02";
227
  constant PC_REV1           : DATA_TYPE := x"01";
228
  constant PC_REV2           : DATA_TYPE := x"00";
229
  constant PC_REV3           : DATA_TYPE := x"FF";
230
 
231 181 jshamlet
  type SP_MODES is ( SP_IDLE, SP_CLR, SP_SET, SP_POP, SP_PUSH );
232
 
233
  type SP_CTRL_TYPE is record
234
    Oper                     : SP_MODES;
235
  end record;
236
 
237
  type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM,
238
                     DATA_WR_REG, DATA_WR_FLAG, DATA_WR_PC );
239
 
240
  type DATA_CTRL_TYPE is record
241
    Src                      : DP_MODES;
242
    Reg                      : SUBOP_TYPE;
243
  end record;
244
 
245 182 jshamlet
  constant PC_LSB            : SUBOP_TYPE := "000";
246
  constant PC_MSB            : SUBOP_TYPE := "001";
247
 
248 181 jshamlet
  type INT_CTRL_TYPE is record
249
    Mask_Set                 : std_logic;
250
    Soft_Ints                : INTERRUPT_BUNDLE;
251
    Incr_ISR                 : std_logic;
252
  end record;
253
 
254 185 jshamlet
  -- Most of the ALU instructions are the same as their Opcode equivalents,
255
  --  with exceptions for IDLE, UPP2, RFLG, RSP, and GMSK, which perform
256
  --  internal operations not otherwise exposed by the instruction set.
257 181 jshamlet
  constant ALU_INC           : OPCODE_TYPE := "00000"; -- x"00"
258
  constant ALU_ADC           : OPCODE_TYPE := "00001"; -- x"01"
259
  constant ALU_TX0           : OPCODE_TYPE := "00010"; -- x"02"
260
  constant ALU_OR            : OPCODE_TYPE := "00011"; -- x"03"
261
  constant ALU_AND           : OPCODE_TYPE := "00100"; -- x"04"
262
  constant ALU_XOR           : OPCODE_TYPE := "00101"; -- x"05"
263
  constant ALU_ROL           : OPCODE_TYPE := "00110"; -- x"06"
264
  constant ALU_ROR           : OPCODE_TYPE := "00111"; -- x"07"
265
  constant ALU_DEC           : OPCODE_TYPE := "01000"; -- x"08"
266
  constant ALU_SBC           : OPCODE_TYPE := "01001"; -- x"09"
267
  constant ALU_ADD           : OPCODE_TYPE := "01010"; -- x"0A"
268
  constant ALU_STP           : OPCODE_TYPE := "01011"; -- x"0B"
269
  constant ALU_BTT           : OPCODE_TYPE := "01100"; -- x"0C"
270
  constant ALU_CLP           : OPCODE_TYPE := "01101"; -- x"0D"
271
  constant ALU_T0X           : OPCODE_TYPE := "01110"; -- x"0E"
272
  constant ALU_CMP           : OPCODE_TYPE := "01111"; -- x"0F"
273
  constant ALU_POP           : OPCODE_TYPE := "10001"; -- x"11"
274
  constant ALU_MUL           : OPCODE_TYPE := "10110"; -- x"16"
275
  constant ALU_UPP           : OPCODE_TYPE := "11000"; -- x"18"
276
  constant ALU_LDI           : OPCODE_TYPE := "11100"; -- x"1C"
277
 
278
  constant ALU_IDLE          : OPCODE_TYPE := "10000"; -- x"10"
279
  constant ALU_UPP2          : OPCODE_TYPE := "10010"; -- x"12"
280
  constant ALU_RFLG          : OPCODE_TYPE := "10011"; -- x"13"
281 185 jshamlet
  constant ALU_RSP           : OPCODE_TYPE := "10111"; -- x"17"
282
  constant ALU_GMSK          : OPCODE_TYPE := "11111"; -- x"1F"
283 181 jshamlet
 
284 185 jshamlet
  -- These should match the assembler's definitions for the flags
285
  constant PSR_Z             : integer := 0;
286
  constant PSR_C             : integer := 1;
287
  constant PSR_N             : integer := 2;
288
  constant PSR_I             : integer := 3;
289
  constant PSR_GP4           : integer := 4;
290 186 jshamlet
  constant PSR_GP5           : integer := 5;
291
  constant PSR_GP6           : integer := 6;
292
  constant PSR_GP7           : integer := 7;
293
 
294
  type ALU_CTRL_TYPE is record
295
    Oper                     : OPCODE_TYPE;
296
    Reg                      : SUBOP_TYPE;
297
  end record;
298
 
299
  constant ACCUM             : SUBOP_TYPE := "000";
300
 
301
  type REGFILE_TYPE is array (0 to 7) of DATA_TYPE;
302
 
303
  subtype FLAG_TYPE is DATA_TYPE;
304
 
305 227 jshamlet
end package;
306 186 jshamlet
 
307
package body Open8_pkg is
308 189 jshamlet
 
309
  -- The ceil_log2 function returns the minimum register width required to
310
  --  hold the supplied integer.
311
  function ceil_log2 (x : in natural) return natural is
312
    variable retval          : natural;
313
  begin
314
    retval                   := 1;
315
    while ((2**retval) - 1) < x loop
316
      retval                 := retval + 1;
317
    end loop;
318
    return retval;
319 227 jshamlet
  end function;
320 189 jshamlet
 
321 186 jshamlet
end package body;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.