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[/] [open8_urisc/] [trunk/] [VHDL/] [fifo_1k_core.vhd] - Blame information for rev 329

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1 207 jshamlet
-- megafunction wizard: %FIFO%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: scfifo 
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-- ============================================================
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-- File Name: fifo_1k_core.vhd
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-- Megafunction Name(s):
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--                      scfifo
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--
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-- Simulation Library Files(s):
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--                      altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2013 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions 
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--and other software and tools, and its AMPP partner logic 
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--functions, and any output files from any of the foregoing 
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--(including device programming or simulation files), and any 
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--associated documentation or information are expressly subject 
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--to the terms and conditions of the Altera Program License 
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--Subscription Agreement, Altera MegaCore Function License 
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--Agreement, or other applicable license agreement, including, 
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--without limitation, that your use is for the sole purpose of 
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--programming logic devices manufactured by Altera and sold by 
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--Altera or its authorized distributors.  Please refer to the 
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY fifo_1k_core IS
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        PORT
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        (
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                aclr            : IN STD_LOGIC ;
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                clock           : IN STD_LOGIC ;
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                data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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                rdreq           : IN STD_LOGIC ;
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                wrreq           : IN STD_LOGIC ;
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                almost_full             : OUT STD_LOGIC ;
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                empty           : OUT STD_LOGIC ;
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                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
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        );
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END fifo_1k_core;
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ARCHITECTURE SYN OF fifo_1k_core IS
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        SIGNAL sub_wire0        : STD_LOGIC ;
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        SIGNAL sub_wire1        : STD_LOGIC ;
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        SIGNAL sub_wire2        : STD_LOGIC_VECTOR (7 DOWNTO 0);
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        COMPONENT scfifo
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        GENERIC (
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                add_ram_output_register         : STRING;
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                almost_full_value               : NATURAL;
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                intended_device_family          : STRING;
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                lpm_numwords            : NATURAL;
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                lpm_showahead           : STRING;
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                lpm_type                : STRING;
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                lpm_width               : NATURAL;
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                lpm_widthu              : NATURAL;
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                overflow_checking               : STRING;
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                underflow_checking              : STRING;
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                use_eab         : STRING
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        );
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        PORT (
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                        aclr    : IN STD_LOGIC ;
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                        almost_full     : OUT STD_LOGIC ;
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                        clock   : IN STD_LOGIC ;
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                        data    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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                        rdreq   : IN STD_LOGIC ;
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                        empty   : OUT STD_LOGIC ;
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                        q       : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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                        wrreq   : IN STD_LOGIC
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        );
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        END COMPONENT;
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BEGIN
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        almost_full    <= sub_wire0;
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        empty    <= sub_wire1;
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        q    <= sub_wire2(7 DOWNTO 0);
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        scfifo_component : scfifo
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        GENERIC MAP (
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                add_ram_output_register => "OFF",
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                almost_full_value => 922,
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                intended_device_family => "Cyclone IV GX",
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                lpm_numwords => 1024,
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                lpm_showahead => "OFF",
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                lpm_type => "scfifo",
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                lpm_width => 8,
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                lpm_widthu => 10,
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                overflow_checking => "ON",
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                underflow_checking => "ON",
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                use_eab => "ON"
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        )
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        PORT MAP (
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                aclr => aclr,
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                clock => clock,
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                data => data,
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                rdreq => rdreq,
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                wrreq => wrreq,
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                almost_full => sub_wire0,
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                empty => sub_wire1,
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                q => sub_wire2
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        );
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
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-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
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-- Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
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-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "922"
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-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
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-- Retrieval info: PRIVATE: Clock NUMERIC "0"
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-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
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-- Retrieval info: PRIVATE: Empty NUMERIC "1"
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-- Retrieval info: PRIVATE: Full NUMERIC "0"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
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-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
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-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
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-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
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-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
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-- Retrieval info: PRIVATE: Width NUMERIC "8"
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-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
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-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
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-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
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-- Retrieval info: PRIVATE: output_width NUMERIC "8"
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-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
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-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
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-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
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-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
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-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
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-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
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-- Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "922"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
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-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
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-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
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-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
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-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
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-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
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-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
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-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
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-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
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-- Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
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-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
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-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
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-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
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-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
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-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
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-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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-- Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
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-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
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-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_core.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_core.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_core.cmp FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_core.bsf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL o8_sync_xmit_fifo_inst.vhd FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k_core_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: altera_mf

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